Senior Digital Verif Engineer - Real-Time ASICs | Equity

Creandum; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Equity & Ownership

Proximity Bonus

Retirement Benefits

Competitive Salary

Job summary

OLIX is seeking highly skilled Senior / Staff Digital Verification Engineers to own the functional correctness of high-speed data-processing silicon, from early algorithm modelling through RTL sign-off and silicon bring-up. The role sits at the intersection of digital, optical, and mixed-signal hardware and requires strong verification expertise.

You will lead verification across high-throughput pipelines, develop advanced environments, and collaborate with multiple teams to ensure robust,

Qualifications

• 5+ years of hands-on experience in digital verification for high-performance ASICs or SoCs.
• Ownership of verification for at least one complex block or subsystem processing continuous real-time data streams.
• Strong proficiency in SystemVerilog, assertions (SVA), and modern verification methodologies (e.g. UVM, CocoTB).
• Proven experience verifying designs operating in GHz-class clock domains, including CDC/RDC analysis.
• Familiarity with RTL simulation, formal verification, linting, CDC/RDC, STA, UPF/CPF, and gate-level simulation.
• Experience verifying high-speed IP such as SerDes, DDR/HBM, PCIe, Ethernet, or similar interfaces.
• Proficiency with MATLAB/Simulink or Python/NumPy for algorithm modelling, fixed-point analysis, and test-vector generation.
• Solid grounding in digital design principles, computer architecture, DSP fundamentals, and semiconductor basics.
• Clear communicator who collaborates effectively across disciplines.

Responsibilities

• Own end-to-end verification of high-throughput digital pipelines supporting multi-GSPS input rates, continuous streaming data paths, deep pipelining, and robust hand-shaking in advanced CMOS nodes.
• Develop and maintain comprehensive verification environments using SystemVerilog/UVM, including constrained-random testing, coverage closure, and regression automation.
• Define and implement assertion-based verification strategies for control logic, data-path correctness, CDC/RDC, and protocol compliance.
• Apply formal verification techniques (property checking, assertions, equivalence checking) to complement simulation-based verification and accelerate bug discovery.
• Model and validate algorithms using MATLAB/Simulink or Python, ensuring functional equivalence from algorithmic models through RTL and gate-level sign-off.
• Support FPGA prototyping and silicon bring-up by developing targeted testcases, debug strategies, and post-silicon validation plans.
• Collaborate closely with digital design, optical-hardware, mixed-signal, and software teams to ensure correct integration across clock domains, interfaces, and firmware abstractions.
• Analyse verification results to identify root causes, drive design fixes, and improve verification efficiency and reuse.
• Contribute to verification methodology development, documentation, and design/verification reviews; mentor junior engineers where appropriate.

Skills

SystemVerilog/UVM

Assertions (SVA)

GHz clock domains

MATLAB/Simulink

Python/NumPy

Tools

Jasper

Job description

OLIX is seeking highly skilled Senior / Staff Digital Verification Engineers to own the functional correctness of high-speed data-processing silicon, from early algorithm modelling through RTL sign-off and silicon bring-up. The role sits at the intersection of digital, optical, and mixed-signal hardware and requires strong verification expertise.

You will lead verification across high-throughput pipelines, develop advanced environments, and collaborate with multiple teams to ensure robust,