Senior Digital Design Architect - SoC Lead

Renesas; San Jose (CA); On-site; USD 190,000 - 240,000; Full time

Benefits offered by this job

Medical, dental, vision

Health Savings Account

Life insurance

AD&D

Paid time off

Job summary

Renesas is seeking a Principal Digital Design Engineer in San Jose to architect, design and implement the digital and mixed-signal IC. You will work with teams in the United States and China across all development phases, delivering high-quality silicon on time and within cost targets.

The role requires strong leadership, hands-on RTL and timing expertise, and the ability to document designs, debug silicon, and support production and applications. A background in AI-enabled workflows is a plus.

Qualifications

• Education: MSEE/PhD with 8+ years experience or BSEE with 12+ years experience.
• Experience in SOC architecture and interfaces – USB, I2C/I3C, SPI, UART.
• Knowledge of SRAM/OTP/MTP/EE Flash memories.
• Hands-on in chip architecture, RTL, synthesis, DFT and timing check.
• Strong communication and teamwork skills.
• AI-savvy and able to leverage AI in daily work.
• Bilingual and Mandarin fluency would be a plus.
• DDR DRAM and Flash memory knowledge would be a plus.
• Mixed-signal chip development experience is highly preferred.
• Project management skills are highly preferred.

Responsibilities

• Architect, design and implement the digital and mixed-signal IC.
• Collaborate with teams in the US and China across development stages.
• Provide design documentation, silicon evaluation, debugging and test support.
• Involve in technology requirements and future product definitions.

Skills

SOC architecture

AHB/APB/AXI

Bus matrix & protocols

Embedded memories

Design flow

Communication & teamwork

AI in daily work

Bilingual Mandarin (plus)

DDR DRAM knowledge

Mixed-signal experience

Project management

Education

MSEE or PhD in Electrical Engineering

BSEE in Electrical Engineering

Job description

Renesas is seeking a Principal Digital Design Engineer in San Jose to architect, design and implement the digital and mixed-signal IC. You will work with teams in the United States and China across all development phases, delivering high-quality silicon on time and within cost targets.

The role requires strong leadership, hands-on RTL and timing expertise, and the ability to document designs, debug silicon, and support production and applications. A background in AI-enabled workflows is a plus.