Senior Analog IC Engineer - High-Performance Mixed-Signal

Renesas; San Jose (CA); On-site; USD 135,000 - 160,000; Full time

Job summary

Renesas Electronics is seeking a Senior Analog Engineer to join our Analog Design team in San Jose. You will design, simulate, verify, and develop high-performance analog and mixed-signal ICs for automotive, industrial, and power management applications, collaborating with global engineers.

Responsibilities include transistor-level circuit design and optimization, building precision references, op-amps, LDOs, bias circuits, and supporting layout, silicon validation, and reliability testing.

Qualifications

• Deep understanding of CMOS device physics and analog circuit fundamentals.
• Experience with transistor-level circuit design, simulation, and verification.
• Hands-on experience with Cadence Virtuoso and Spectre for analog/mixed-signal blocks.

Responsibilities

• Circuit Design & Optimization: transistor-level design, simulation and optimization for analog/mixed-signal blocks.
• Block-Level Architecture: develop precision references, bias circuits, op-amps, LDOs and related analog circuits.
• Layout & Physical Design Support: collaborate with layout engineers to ensure robust analog layouts.
• Silicon Validation: analyze measurements, conduct lab evaluation and drive improvements.
• Qualification & Reliability: support product qualification and reliability testing.

Skills

CMOS device physics

Analog circuit fundamentals

Education

MS or PhD in Electrical Engineering (or B.S. with equivalent)

Tools

Cadence Virtuoso

Spectre

Job description

Renesas Electronics is seeking a Senior Analog Engineer to join our Analog Design team in San Jose. You will design, simulate, verify, and develop high-performance analog and mixed-signal ICs for automotive, industrial, and power management applications, collaborating with global engineers.

Responsibilities include transistor-level circuit design and optimization, building precision references, op-amps, LDOs, bias circuits, and supporting layout, silicon validation, and reliability testing.