Senior Digital ASIC Architect: Lead High-Impact Chip Design

The Charles Stark Draper Laboratory, Inc.; Cambridge (MA); On-site; USD 82,000 - 220,000; Full time

Benefits offered by this job

Workplace flexibility

Employee clubs

Health and finance workshops

Off-site social events

Discounts to local museums

Job summary

The Charles Stark Draper Laboratory, Inc. in Cambridge, MA is seeking a Senior Digital ASIC Architect to lead digital IC design from concept through delivery.

You will collaborate with Analog and Digital teams to optimize architectures and manage SOC trades that balance performance, power, and cost. Responsibilities include architectural definition, verification planning, and guiding both design and test flows while mentoring engineers and communicating with customers.

Qualifications

• Bachelor's degree in Engineering or related field; Master's preferred.
• 5-7 years of ASIC hardware engineering experience.
• Experience with SystemVerilog and mixed-signal design.
• Ability to lead small technical teams and communicate clearly.

Responsibilities

• Independently drive IC-based designs from concept to delivery.
• Develop chip-level IC requirements from customer needs.
• Design and simulate circuits using MATLAB, Simulink, SystemVerilog and SystemC.
• Review and mentor circuit designers and adjust requirements as needed.
• Lead multi-disciplinary design teams and present technical solutions to leadership.

Skills

IC design

SystemVerilog

SoC architectures

Team leadership

Modeling & simulation

Education

Bachelor's degree in Engineering

Master's degree preferred

Tools

Cadence

Genus

Innovus

Tempus

Voltus

SystemVerilog

Job description

The Charles Stark Draper Laboratory, Inc. in Cambridge, MA is seeking a Senior Digital ASIC Architect to lead digital IC design from concept through delivery.

You will collaborate with Analog and Digital teams to optimize architectures and manage SOC trades that balance performance, power, and cost. Responsibilities include architectural definition, verification planning, and guiding both design and test flows while mentoring engineers and communicating with customers.