Senior DFT Power Methodology Engineer

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 196,000 - 368,000; Full time

Job summary

NVIDIA Gruppe is seeking a DFT Engineer to drive innovations in AI for chip design. You will develop low power and thermal solutions, collaborate with diverse teams, and mentor junior engineers.

The ideal candidate holds a BSEE, MSEE, or PhD with extensive experience in DFT design and power analysis. The role also offers competitive salary options ranging from $196,000 to $368,000 based on experience and level.

Qualifications

• 12+ years of experience for BSEE, 10+ for MSEE, or 6+ years for PhD.
• Excellent communication skills and curiosity.
• Experience managing DFT Power Methodology for designs.

Responsibilities

• Develop low power and thermal solutions for manufacturing tests.
• Collaborate with multi-functional teams for improving chip quality.
• Perform post-silicon data analysis for next-gen solutions.

Skills

Experience in DFT design & power

Knowledge in power analysis & thermal analysis

Statistical tools for data analysis

Experience using AI for EDA

Silicon debug and bring-up on ATE or SLT

Strong programming skills

Education

BSEE/MSEE/PhD in relevant fields

Tools

DFT tools

Thermal analysis tools

AI coding harnesses

Job description

Overview

Design-for-X Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions in AI for Chip Design and AI for Predictions in various use cases in manufacturing testing on some of the industry's most complex semiconductor chips.

What You’ll Be Doing

• Innovation in DFT Power, Thermal & Voltage Noise Methodology areas.
• Develop low power & thermal solutions for manufacturing tests at conditions that push the boundaries for data center GPUs.
• Collaborate with multi-functional teams including Product Development & Power Architecture to implement brand-new methodologies for improving outgoing quality of chips.
• Perform post-silicon data analysis for power to architect the next-gen solutions.
• Develop and deploy DFT methodologies for next-generation products using Applied ML & Gen AI solutions.
• Mentor junior engineers on test designs and trade-offs including cost and quality.

What We Need to See

• BSEE (or equivalent experience) with 12+ years, MSEE with 10+ years, or PhD with 6+ years of experience in DFT design & power.
• Understanding of fundamental DFT topics and VLSI areas of power, timing & voltage noise.
• Experience in Power Analysis, Thermal Analysis & IR Drop tools is a plus.
• Experience in application of AI for EDA-related problem-solving is a plus.
• Excellent knowledge in using statistical tools for data analysis & insights.
• Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route and power.
• Experience in silicon debug and bring-up on the ATE or SLT platforms.
• Ability to think like a programmer so that this can be translated into action using AI coding harnesses.
• Outstanding written and oral communication skills with curiosity to work on rare challenges.

Ways to Stand Out

• Experience in managing DFT Power Methodology for designs.
• Experience in post-silicon debug for thermal & IR Drop.
• Good understanding of technology and passion about what you do.
• Strong collaborative and interpersonal skills, with proven ability to guide and influence within a dynamic environment.

Benefits

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is $196,000 USD – $310,500 USD for Level 5, and $232,000 USD – $368,000 USD for Level 6. You will also be eligible for equity and benefits.

Equal Opportunity Employer

NVIDIA is committed to fostering an inclusive work environment and is proud to be an equal opportunity employer. We do not discriminate based on race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.