Senior DFT Engineer - End-to-End ASIC/FPGA Test Architect

Roguebeam; Seattle (WA); On-site; USD 150,000 - 190,000; Full time

Job summary

Roguebeam in Seattle is seeking a Senior DFT Engineer to own design-for-test architecture for phased-array ASIC/FPGA solutions. You will define test strategies, insert and verify DFT structures, and drive coverage, ATPG, and lab bring-up across RTL, synthesis, and PD teams.

You will lead automated DFT flows with TCL/Python, optimize test time and power, and mentor junior engineers as the team grows. This role sits at the intersection of design and test in a hands-on startup environment.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 7–10 years of relevant DFT experience on ASICs or large FPGAs.
• Hands-on experience with industry DFT tools (e.g., Siemens Tessent, Synopsys TestMAX) including scan insertion, compression, MBIST, and ATPG.
• Proven ability to verify DFT in simulation and take patterns to silicon or FPGA.
• Solid understanding of RTL (SystemVerilog/Verilog), STA/test-mode constraints, and CDC/lint implications of DFT logic.
• Demonstrated ability to work across RTL, synthesis, PD, and test engineering.

Responsibilities

• Define and implement hierarchical and full-chip DFT architecture for digital beamforming, adaptive, and high-speed interface blocks (scan, compression, MBIST/repair, LBIST, JTAG / IEEE 1149.1/1500/1687, on-chip debug)
• Insert, verify, and sign off DFT structures; drive coverage, DRC, and pattern quality
• Generate and validate ATPG patterns (stuck-at, transition, and other required fault models); optimize pattern count, test time, and test power
• Run and debug gate-level simulations of test modes; deliver vectors and support FPGA/ASIC bring-up and ATE
• Partner with RTL, synthesis/timing, and physical design so scan and test clocks close timing and do not break PPA
• Automate DFT flows (Tcl/Python); own specs, coverage reports, and silicon diagnosis notes
• Contribute to technical strategy, design reviews, documentation, and mentoring as the team grows

Skills

DFT engineering

ASIC/FPGA testing

RTL Verilog/SystemVerilog

ATPG and scan

Scripting (Python/Tcl)

Test automation

Education

Bachelor's degree in Electrical/Computer Engineering

MSc or PhD in EE/CE

Tools

Siemens Tessent

Synopsys TestMAX

JTAG/IEEE 1149.x

Job description

Roguebeam in Seattle is seeking a Senior DFT Engineer to own design-for-test architecture for phased-array ASIC/FPGA solutions. You will define test strategies, insert and verify DFT structures, and drive coverage, ATPG, and lab bring-up across RTL, synthesis, and PD teams.

You will lead automated DFT flows with TCL/Python, optimize test time and power, and mentor junior engineers as the team grows. This role sits at the intersection of design and test in a hands-on startup environment.