Senior Physical Design Engineer: End-to-End ASIC/FPGA

Roguebeam; Seattle (WA); On-site; USD 180,000 - 240,000; Full time

Job summary

Roguebeam is seeking a Senior Physical Design Engineer to own block- and chip-level implementation from netlist to GDS, with FPGA P&R support, for phased-array solutions. You will floorplan, place, clock, route, and sign off silicon that carries digital beamforming and adaptive processing.

You will collaborate end-to-end on timing, CTS, and verification, integrating memories, high-speed interfaces, and DFT structures.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering.
• 7–10 years of physical design experience (RTL-to-GDS) on ASICs; FPGA P&R experience a plus.
• Hands-on with industry PD tools (e.g., Innovus, ICC2/Fusion Compiler, PrimeTime, Calibre or equivalent)
• Proven timing closure, CTS, and physical verification on multi-clock, high-utilization designs
• Scripting (Tcl/Python) and ability to debug tool and design issues independently
• Demonstrated ability to work with front-end and DFT so implementation matches system performance goals

Responsibilities

• Execute physical design for DSP, beamforming, and interface partitions and for top level: floorplan, power, placement, CTS, route, optimization
• Close timing with PD tools in partnership with the synthesis/timing owner; implement timing and functional ECOs
• Integrate memories, I/Os, high-speed interfaces, and DFT structures; manage congestion and utilization on high-throughput datapaths
• Run physical verification (DRC/LVS/antenna) and support EM/IR sign-off
• Collaborate with RTL, synthesis/STA, and DFT on constraints, scan timing, and design changes that affect layout
• Support FPGA P&R and timing when prototypes are used before or alongside ASIC
• Contribute to technical strategy, design reviews, documentation, and mentoring as the team grows

Skills

Timing closure

Scripting (Tcl/Python)

DFT/verification

Multi-clock designs

RTL-to-GDS

Front-end/DFT collaboration

Education

Bachelor's degree in Electrical/Computer Engineering

MSc or PhD in EE/CE

Tools

Innovus

ICC2/Fusion Compiler

PrimeTime

Calibre

Job description

Roguebeam is seeking a Senior Physical Design Engineer to own block- and chip-level implementation from netlist to GDS, with FPGA P&R support, for phased-array solutions. You will floorplan, place, clock, route, and sign off silicon that carries digital beamforming and adaptive processing.

You will collaborate end-to-end on timing, CTS, and verification, integrating memories, high-speed interfaces, and DFT structures.