Senior DFT Engineer – AI-Driven ASIC Fault Coverage

Amazon Kuiper Manufacturing Enterprises LLC; Bonita (CA); On-site; USD 185,000 - 250,000; Full time

Job summary

Amazon Kuiper Manufacturing Enterprises LLC seeks a senior DFT engineer to shape the digital chip SOCs for LEO satellite communications. You will work with RTL/ASIC teams across sites to define DFT architecture, MBIST and JTAG controls, and AI-assisted flows to improve test coverage on CMOS nodes.

This role requires a strong background in DFT methods, 5+ years of experience, and collaboration with RFIC teams to ensure robust, high-yield devices.

Qualifications

• Bachelor's degree in Electrical/Communications Engineering or related field.
• 5+ years of experience in advanced DFT techniques for deep sub-micron nodes.
• Experience implementing DFT methodology and developing automated scripts for DFT Insertion and Validation.

Responsibilities

• Architect and define DFT solutions adapted to the specific use of various LEO's chips.
• Contribute to the improvement and customization of IPs and DFT methodology while embracing AI flow.
• Work with the ASIC design teams in all the sites to incorporate DFT logic like MBIST, clock controls and JTAG controllers.
• Work with RFIC teams to ensure maximum fault coverage on the custom RF blocks.
• Ensure that blocks meet DFT, timing and power targets by working closely with the implementation team.
• Work closely with the Test engineering team to help translate the ATE patterns to tester format.
• Work with the test team to do jointly bring up the digital portions of the LEO chips.

Skills

DFT techniques

Automation scripting for DFT

MBIST

JTAG controllers

RFIC collaboration

Education

Bachelor's degree in Electrical/Communications Engineering

Master's or Ph.D in Electrical/Communications Engineering

Tools

Logic BIST

Job description

Amazon Kuiper Manufacturing Enterprises LLC seeks a senior DFT engineer to shape the digital chip SOCs for LEO satellite communications. You will work with RTL/ASIC teams across sites to define DFT architecture, MBIST and JTAG controls, and AI-assisted flows to improve test coverage on CMOS nodes.

This role requires a strong background in DFT methods, 5+ years of experience, and collaboration with RFIC teams to ensure robust, high-yield devices.