Senior DFT Engineer

MetAntz; Sunnyvale, Northern (CA, KY); Híbrido; USD 140.000 - 190.000; Jornada completa

Descripción de la vacante

QFocus Technologies in Sunnyvale, CA seeks a Senior DFT Engineer to define, architect, and execute robust DFT strategies for high‑performance SoCs and ASICs, collaborating with frontend, physical design, verification, and product teams.

You will drive Scan, ATPG, MBIST, and JTAG implementations, translate pre-silicon patterns to tester formats, and support post‑silicon bring‑up to maximize yield. Strong Verilog/SystemVerilog and scripting proficiency required.

Formación

• 3+ years hands-on DFT in advanced SoC/ASIC development.
• Strong proficiency in Verilog/SystemVerilog for DFT integration, wrappers, and debugging.
• Experience with scan synthesis, boundary scan, and compressed scan architectures.
• Deep experience generating, debugging, and fault-grading Stuck-at/At-speed patterns.

Responsabilidades

• Define and implement comprehensive DFT architectures including Scan, ATPG, MBIST, and JTAG.
• Perform Scan Chain Insertion, stitching, and optimization for timing closure and power-grid compatibility.
• Integrate MBIST controllers, repair mechanisms, and memory test routines.
• Generate high-coverage ATPG patterns (Stuck-at, At-Speed, Cell-Aware).
• Execute Verilog/SystemVerilog simulations for gate-level DFT validation (SDF).
• Run DFT linting and rule checks using SpyGlass DFT, Tessent, Modus, or TetraMAX.
• Translate pre-silicon ATPG/MBIST patterns into tester formats for ATE deployment.
• Support post-silicon bring-up and yield ramp with pattern conversion and debugging.

Conocimientos

DFT architectures

ATPG patterns

MBIST

JTAG

Scan insertion

Verilog

SystemVerilog

SDF simulation

Scripting (Python/Tcl)

Herramientas

SpyGlass DFT

Tessent

Modus

TetraMAX

Descripción del empleo

Job Overview

As a Senior DFT Engineer at QFocus Technologies, you will be responsible for defining, architecting, and executing robust Design-for-Test strategies for high-performance SoCs and ASICs. You will work closely with front-end design, physical design, verification, and product engineering teams to ensure high test coverage, optimal silicon quality, and streamlined post-silicon manufacturing test enablement.

Key Responsibilities

Pre-Silicon Execution

• Define and implement comprehensive DFT architectures including Scan, ATPG, MBIST, and JTAG (IEEE standards 1149.1, 1500, 1687 IJTAG).
• Perform Scan Chain Insertion, stitching, and optimization to ensure timing closure and power grid compatibility.
• Integrate Memory BIST (MBIST) controllers, repair mechanisms, and custom memory test routines.
• Generate high-coverage Automatic Test Pattern Generation (ATPG) patterns, including Stuck-at, At-Speed (Transition, Path Delay), and Cell-Aware testing.
• Execute Verilog, SystemVerilog simulations for gate-level DFT validation, ensuring timing and vector cleanliness (SDF simulation).
• Run DFT linting and rule checking using industry-standard tools (e.g., SpyGlass DFT, Tessent, Modus, or TetraMAX).

Post-Silicon Production & Bring-Up

• Translate pre-silicon ATPG and MBIST patterns into tester formats (e.g., WGL, STIL) for ATE (Automatic Test Equipment) deployment.
• Support post-silicon bring-up in the lab, debugging first-silicon DFT features, pattern conversion, and silicon failures.
• Collaborate with Product and Test Engineering (PTE) teams to optimize test time, diagnose failure modes, and boost manufacturing yield.

Required Qualifications

• Experience: 3+ years of hands-on DFT experience in advanced SoC, ASIC development nodes.
• Verilog & SystemVerilog: Strong proficiency in Hardware Description Languages for DFT integration, wrapper creation, and simulation debugging.
• Scan Insertion: Hands-on experience with scan synthesis, compressed scan architectures (EDT, SmartTest), and boundary scan integration.
• ATPG: Deep experience generating, debugging, and fault-grading Stuck-at, At-speed, and fault-model test patterns.
• MBIST: Proven experience with memory BIST insertion, MBIST architecture, and memory repair schemes.
• JTAG: Solid understanding of IEEE 1149.1 standards, TAP controllers, and board, chip-level test logic integration.
• Post-Silicon Support: Direct experience bringing up patterns on target silicon and supporting production yield ramp.

Preferred Skills

• Familiarity with scripting languages (Tcl, Python, or Perl) for automation of DFT flows.
• Knowledge of advanced DFT concepts like High-Speed IO testing, SerDes loopback, or Analog DFT.
• Understanding of synthesis tools (Synopsys Design Compiler, Cadence Genus) and static timing analysis (STA) constraint creation for DFT modes.

Location

Sunnyvale, California, USA