Senior DfT Engineer

NXP Semiconductors; Chandler (AZ); On-site; USD 120,000 - 160,000; Full time

Job summary

NXP Semiconductors in Chandler, AZ is seeking a Senior DfT Engineer to join a seasoned team. You will define DfT requirements with cross-functional leads, insert DfT into analog/mixed-signal IPs and complex digital logic, and ensure high-quality RTL and DV coverage.

You will drive verification plans, write tests, and assist test engineers during silicon bring-up and field issues. The ideal candidate holds a Master’s in Electrical Engineering with 3+ years in DfT or digital design, is able to

Qualifications

• Master's degree in Electrical Engineering or related field.
• 3+ years in DfT, digital design or architecture.
• Willing to relocate to the Phoenix Metro area and be present 3 days/week at the Chandler office.
• Strong problem solving, teamwork, planning and communication skills.

Responsibilities

• Collaborate with Product Definer, Analog/Digital Design Leads, Test Lead and others to define DfT requirements for chip blocks (functional mode, debug mode, ATPG).
• Research and apply DfT techniques for analog/mixed-signal IPs, macros, and complex digital logic.
• Contribute to RTL quality using Verilog/SystemVerilog and DV planning for chip-top verification.
• Define and execute Verification Plan for implemented features; create tests and debug to pass DV flows.

Skills

Verilog

SystemVerilog

RTL design

DfT design

Digital verification

Debugging

Communication skills

Education

Master's degree in Electrical Engineering

Job description

## Senior DfT EngineerApplylocations: Chandler (Office)time type: Full timeposted on: Posted Todayjob requisition id: R-10064841As a DfT engineer, you will join a highly experienced team. Your key responsibilities will be:1) Closely collaborate with Product Definer, Analog Design Lead, Digital Design Lead, Test Lead, Product Engineer, Quality Engineer, Validation Engineer – to identify the superset of requirements for Testability of the chip (Functional mode, Debug mode, ATPG).2) Gain deep understanding on existing and innovative ways to insert DfT for complex analog and mixed-signal IPs, standard Macros (RAM, ROM, NVM, ADC, DAC) and complex digital logic.3) High-quality of RTL design using Verilog and System-Verilog4) Define Verification Plan for the implemented features and write tests, debug and get those passing at Chiptop level DV environment5) Scan insertion, optimization, length balancing, P&R-aware rerouting of chains, Test-Point insertion, ATPG patterns generation, simulation and debug6) Support Test Engineers during debug of patterns on new silicon, and on customer returns7) Participate in Design & Test Review meetings and support the team for DfT 8) Generate comprehensive DfT Architecture & Design documentation and maintain it to match later updates9) Troubleshoot and resolve issues related to DfT throughout the development lifecycle 10) Stay updated with the latest industry trends, tools, and methodologies in DfT design**Job Qualification:*** Master's degree (MSEE) with majority of courses relevant to Digital Design, RTL coding, DfT, Computer Architecture, Digital Verification.* Minimum 3 years of experience in similar role of DfT, Digital Design & Architecture. Seeking 3-8 years total experience for this role* Willing to relocate to Phoenix Metro area (Arizona) and minimum 3 days per week full-day presence in NXP's Chandler office* Excellent on problem-solving, teamwork, planning, organizing, attention to detail and communication skills.More information about NXP in the United States...NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.