Project Design Lead (EX)

Nexperia

San Jose (CA)

Hybrid

USD 169,884 - 207,636

Full time

14 days+

Get more replies from employers

Send a job-specific resume in minutes.

Benefits offered by this job

Telecommuting up to 3 days per week

Job summary

Nexperia is seeking a Project Design Lead in San Jose, CA, to design digital logic circuits and ensure design verification. The role requires a Master’s degree in Electrical Engineering or a related field, and 2 years of experience in digital IC design and verification. Candidates must demonstrate experience with simulation tools, digital design practices, and collaboration in cross-functional teams. The position offers a competitive salary of $188,760 annually with up to 3 days of telecommuting permitted.

Qualifications

  • Must have a Master’s degree in Electrical Engineering, Computer Engineering, or related field.
  • 2 years of experience in digital IC design and verification or 4 years with a Bachelor's degree.
  • Experience with AI/ML tools applied in digital design automation.

Responsibilities

  • Design digital logic circuits for mixed-signal IC integrations.
  • Perform static design verification and analyze timing reports.
  • Collaborate with firmware teams for pre-silicon validation.

Skills

Digital circuit design and verification
Using simulation tools (Cadence Xcelium)
RTL design (Verilog/SystemVerilog)
Static design checks (Lint, CDC, RDC)
FPGA prototyping and validation
AI/ML tools in design automation
Post-silicon debugging
Collaboration with cross-functional teams

Education

Master’s degree in Electrical or Computer Engineering
Bachelor’s degree in related field

Tools

Cadence Xcelium
SystemVerilog
Verilog

Job description

Overview

Nexperia is a world-class company in semiconductor development and in-house production. A proven global player with an entrepreneurial mentality. At our core is a 13,000+ strong international network with a singular focus. Built on passion and commitment to our work, belief in our goals and a drive to succeed regardless of the challenges we face. We support, reward and challenge individuals equally, in a dynamic and energetic environment.

Role

Project Design Lead, Nexperia USA Inc., San Jose, CA: Design digital logic circuits for integration into mixed-signal ICs, including finite state machines, control logic, data path components, and interface blocks, based on product requirements and system architecture specifications. Perform static design verification including Lint checking to ensure code quality, Clock Domain Crossing (CDC) analysis to validate synchronization of asynchronous clocks and Reset Domain Crossing (RDC) analysis to confirm correct handling of resets across domains. Analyze simulation, synthesis, and timing reports to validate design quality and correct operation under different process-voltage-temperature (PVT) conditions. Conduct applied research into machine learning (ML) or artificial intelligence (AI) techniques for the purpose of improving digital design and verification flows, including automation of test generation, design space exploration, and bug triage. Translate system and product definition documents into digital architecture, block-level specifications, and micro-architecture definitions, and document digital design implementation details. Generate behavioral models of analog or mixed-signal components using high-level modeling techniques (e.g., SystemVerilog, Verilog-A) to enable mixed-signal simulation and validate digital-analog interaction early in the design process. Build Field Programmable Gate Array (FPGA) prototypes for digital logic emulation, perform functional tests using application-level scenarios, and collaborate with firmware teams for pre-silicon validation and debugging. Participate in post-silicon bring-up by analyzing lab measurements and test data, identifying root causes of issues, comparing silicon behavior with simulation models, and recommending fixes or design changes. Develop scripts, ML models, or AI-based tools to optimize verification workflows, automate debugging tasks, extract features from simulation datasets, and enhance RTL code quality and coverage metrics. Collaborate with cross-functional teams including analog designers, system engineers, software developers, and CAD/methodology engineers to define requirements and integrate AI-enhanced solutions into production design workflows.

Qualifications

Employment type and compensation: Full time employment, Monday – Friday, 40 hours per week, $188,760 per year.

Minimum Requirements

Must have a Master’s degree in Electrical Engineering, Computer Engineering, or a related field and 2 years of experience in digital IC design and verification. Alternatively, a Bachelor’s degree and 4 years of experience. Must have 2 years of experience in each of the following:

  • Experience with digital circuit design and verification for mixed-signal chip products
  • Experience using simulation tools, including Cadence Xcelium, to debug RTL and analyze RTL code coverage
  • Experience working in at least one project in verification environment and platform setup
  • Experience working in at least one project in digital function design
  • Experience with RTL design using Verilog or SystemVerilog
  • Experience with static design checks including Lint, CDC, and RDC
  • Experience with FPGA prototyping and pre-silicon validation
  • Experience with post-silicon debugging
  • Experience using AI/ML tools in digital design automation

Telecommuting permitted up to 3 days per week.

Nexperia is an Equal Opportunity Employer that does not discriminate on the basis of race, color, creed, religion, national origin, ancestry, citizenship status, age, sex or gender (including pregnancy, childbirth and pregnancy-related conditions), gender identity or expression, sexual orientation, marital status, military service and veteran status, physical or mental disability, genetic information, or any other characteristic protected by applicable laws. Nexperia’s management is dedicated to this policy with respect to recruitment, hiring, placement, promotion, transfer, training, compensation, benefits, and general employment practices.

D&I Statement As an equal-opportunity employer, Nexperia values diversity and is committed to inclusive recruitment and a safe work environment. We support employee resource groups.

Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

Mixed Signal Design Verification (MSDV) Engineer
Mixed Signal Design Verification (MSDV) Engineer

Nexperia • Fort Worth (TX), Town of Texas (WI)

On-site
USD 110,000 - 160,000
Health, dental, vision insurance
Retirement plan with company match
Paid time off and holidays
+3
Mixed Signal Design Verification (MSDV) Engineer
Mixed Signal Design Verification (MSDV) Engineer

Nexperia • Dallas (TX), Northern (KY)

Hybrid
USD 110,000 - 160,000
Health, dental, and vision insurance
Retirement plan with company match
Paid time off and holidays
Senior EDA Development Engineer
Senior EDA Development Engineer

Nexperia • Dallas (TX)

On-site
USD 120,000 - 180,000
Digital IP Senior Verification Engineer
Digital IP Senior Verification Engineer

NXP Semiconductors • Austin (TX)

On-site
USD 120,000 - 170,000
Senior EDA Development Engineer
Senior EDA Development Engineer

Nexperia • Fort Worth (TX), Town of Texas (WI)

On-site
USD 120,000 - 180,000
Design Director
Design Director

Nexperia • Dallas (TX)

On-site
USD 150,000 - 200,000
Strong healthcare benefits
Tremendous career growth opportunities
401K with company match
+2
Principal Engineer
Principal Engineer

NXP Semiconductors • United States

On-site
USD 147,000 - 200,000
Senior Staff Digital Design Engineer
Senior Staff Digital Design Engineer

ams-OSRAM USA Inc. • Plano (TX)

On-site
USD 150,000 - 190,000
Senior Engineer I- Design
Senior Engineer I- Design

Microchip Technology Inc. • Chandler (AZ)

On-site
USD 110,000 - 150,000
Physical Design Technical Lead
Physical Design Technical Lead

191 Altera Corporation • San Jose (CA)

On-site
USD 209,000 - 300,000