Senior Digital/AMS Validation and Integration Engineer

NXP Semiconductors; San Jose (CA); On-site; USD 166,200 - 228,500; Full time

Benefits offered by this job

Health insurance

Dental insurance

Vision insurance

401(k)

Paid leave

Job summary

NXP Semiconductors in San Jose is looking for a Senior Digital/AMS Design Engineer to drive complex integration tasks in Automotive SerDes transceivers. Responsibilities include RTL design, timing closure, and silicon validation. Candidates should possess a BSEE/MSEE with 5–8 years of experience in digital design, expertise in SystemVerilog/Verilog, and familiarity with high-speed interfaces. The competitive salary range is $166,200 to $228,500 annually, alongside comprehensive company benefits and a commitment to equal opportunity.

Qualifications

• 5–8+ years of experience in Digital RTL Design or Digital Integration.
• Advanced proficiency in SystemVerilog/Verilog for synthesis.
• Strong understanding of Static Timing Analysis and clock domain crossing.

Responsibilities

• Develop and integrate RTL for control loops, calibration engines, and data paths.
• Define and implement digital interfaces for analog blocks.
• Lead the digital implementation flow and achieve timing closure.

Skills

Digital RTL Design

SystemVerilog/Verilog

Python

Static Timing Analysis

Digital Integration

Education

BSEE/MSEE

Tools

Logic Analyzers

High-speed scopes

JTAG/I2C/SPI protocols

Job description

We are seeking a Senior Digital/AMS Design Engineer to drive the integration of complex digital logic into our industry‑leading Automotive SerDes transceivers. In this role, you will be responsible for the RTL design of the "Digital-Analog Wrapper," ensuring seamless control and data flow between high‑speed analog front‑ends and the DSP/Link‑layer logic. You will own the path from RTL through timing closure and support the validation of that logic in the lab.

Key Responsibilities

• RTL Design & Integration: Develop and integrate RTL (Verilog/SystemVerilog) for control loops, calibration engines, and high‑speed data paths in 10G+ transceivers.
• Mixed‑Signal Interface: Define and implement the digital interface for analog blocks (ADCs, PLLs, Driver stages), ensuring robust signal crossing between asynchronous domains.
• Timing Closure & Synthesis: Lead the digital implementation flow, working closely with the physical design team to achieve timing closure in high‑speed clock domains.
• Silicon Validation: (40% Lab Focus) Partner with the validation team to bring up silicon. Use Python‑based tools to exercise RTL features, debug state machines, and verify registers (CSRs) in real‑time hardware.
• Functional Correctness: Execute block‑level and chip‑level simulations to ensure digital control logic correctly handles analog PVT variations and startup sequences.

Skills & Qualifications

• Education: BSEE/MSEE with 5–8+ years of experience in Digital RTL Design or Digital Integration.
• HDL Expertise: Advanced proficiency in SystemVerilog/Verilog for synthesis.
• Timing & Implementation: Strong understanding of Static Timing Analysis (STA), clock domain crossing (CDC), and constraints (SDC).
• Scripting & Automation: Deep experience with Python or Perl for hardware control, test automation, and data processing.
• Lab Skills: Proficient in using logic analyzers, high‑speed scopes, and JTAG/I2C/SPI protocols for on‑chip debugging.

Preferred Experience

• Experience with 10GBase‑T, ASA, or Automotive Ethernet standards.
• Familiarity with the hand‑off between digital logic and high‑speed Analog Front Ends (AFE).
• Knowledge of DFT (Design for Test) and BIST (Built‑In Self‑Test) insertion for high‑speed links.
• Able to create Verilog‑A models.

The base salary range for this position is as mentioned below per year. We also provide competitive benefits, incentive compensation, and/or equity for certain roles. Company benefits include health, dental, and vision insurance, 401(k), and paid leave. Please note that the base salary range (or hourly rate) is a guideline, and individual total compensation may vary based on a number of factors such as qualifications, skill level, work location, and other business and organizational needs. This base pay range is specific to California and is not applicable to other locations. A reasonable estimate of the base salary range as of the date of this posting is: $166,200 to $228,500 annually.

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity, and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.