High Speed Analog Design Engineer

NXP Semiconductors; Chandler (AZ); On-site; USD 110,000 - 160,000; Full time

Job summary

NXP Semiconductors in Chandler, AZ is seeking an Analog Design Engineer to develop high-speed analog and mixed-signal circuits, including USB and SerDes interfaces, PLLs, and LDOs. You will work hands-on from concept through silicon validation and collaborate with layout teams.

The role requires an MS in EE with 3–5 years IC experience (or PhD with some), strong SI, jitter, and noise analysis, and proficiency with Cadence tools and MATLAB/Simulink. Excellent communication in English is essential.

Qualifications

• MS in Electrical Engineering with 3–5 years IC development experience.
• Strong background in high-speed analog circuit design fundamentals including SI, jitter, noise, bandwidth optimization, stability.

Responsibilities

• Design and validate high-speed analog/mixed-signal circuits from concept to silicon validation.
• Lead and participate in design reviews and mentor junior engineers.
• Collaborate with layout for device placement, matching and EM/IR compliance.
• Develop behavioral models (Verilog-A/AMS) for architecture validation.

Skills

High-speed analog design

Jitter analysis

Signal integrity

Noise analysis

Verilog-A/AMS modeling

Documentation

Education

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Virtuoso

Spectre

MATLAB/Simulink

Job description

## High Speed Analog Design EngineerApplylocations: Chandler (Office)time type: Full timeposted on: Posted Todayjob requisition id: R-10062964**Job Title:** Analog Design Engineer**Job Responsibility:*** Design high-performance analog and mixed-signal circuits, including: High-speed re-drivers(AFE RX Equalization and Tx output line drivers) and High-speed switches for USB applications, Clocking circuits (PLL, frequency multipliers, Jitter conditioning), High Speed IO designs, Precision analog circuits, cap-less LDOs, and low-voltage bandgaps and charge pumps* Hands on circuit design, simulations and documentation from concept to silicon validation* Translate chip-level requirements(data rate, BER, Jitter budget) into detailed block level architectures and detailed sub-block specifications* Develop behavioral models (Verilog-A/AMS) for analog blocks to validate architecture performance* Perform system-level modeling (MATLAB/Simulink) for noise and transfer functions* Conduct design analysis and hand calculations to predict and validate simulation results* Lead and participate in design reviews* Present technical solutions to internal teams and external customers* Collaborate with layout engineers to ensure optimal device placement, matching, EM/IR compliance, shielding, and guard ring implementation* Drive innovation and propose differentiated technical solutions to meet customer and product requirements**Job Qualification:*** MS in Electrical Engineering with 3–5 years of IC development experience, or PhD with 1-2 years of experience* Strong expertise in high-speed analog circuit design fundamentals including Signal integrity, jitter analysis, noise, bandwidth optimization, Stability and frequency compensation techniques* Proven experience in one or more of the following: High-speed interfaces (e.g., SerDes, USB, Ethernet, or similar), Clocking systems (PLL, CDR, frequency synthesis)* Hands-on experience with Cadence IC design tools (Virtuoso, Spectre, etc.) and modeling tools such as MATLAB/Simulink* Solid understanding of device physics and parasitic effects impacting high-speed performance* Strong cross-functional collaboration skills with the ability to operate effectively in a global environment* Excellent verbal and written communication skills* Fluency in English (spoken and written)More information about NXP in the United States...NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.