Senior Analog IC Designer – Hybrid, Stock Options

Powerlattice Technologies Inc; Chandler (AZ); Hybrid; USD 150,000 - 200,000; Full time

Benefits offered by this job

Stock option grant

Benefits package including health, 401

Job summary

PowerLattice Technologies Inc in Chandler, AZ is seeking a Senior or Staff Analog IC Designer to develop high-quality analog and mixed-signal ICs from specification through post-layout verification and silicon validation.

You will collaborate with layout, verification, and silicon validation teams to deliver robust, production-ready designs, with a hybrid work model requiring 3 days onsite.

Qualifications

• 5+ years of hands-on analog design experience.
• Strong foundation in analog circuit theory, device physics, and CMOS tech.
• Experience designing bandgap references, LDOs, oscillators, op-amps, ADCs, and DACs.
• Proficiency with Cadence and other industry-standard tools.
• DC, AC, transient, noise, and corner simulations.
• Reliability, mismatch, and layout-dependent effects.
• Hands-on lab experience including silicon bring-up and debugging.

Responsibilities

• Design and develop core analog and mixed-signal circuit blocks.
• Translate specifications into robust architectures.
• Perform schematic capture, simulation, and optimization.
• Provide layout guidance and collaborate with layout engineers.
• Perform post-layout simulations and validation.
• Participate in design reviews and document designs.
• Support silicon bring-up, evaluation, characterization, and debugging.
• Apply best practices for analog design, verification, and sign-off.

Skills

Analog design

Circuit simulations

CMOS technologies

Device physics

Layout guidance

Education

Bachelor’s degree in Electrical Engineering or related field

Tools

Cadence

Job description

PowerLattice Technologies Inc in Chandler, AZ is seeking a Senior or Staff Analog IC Designer to develop high-quality analog and mixed-signal ICs from specification through post-layout verification and silicon validation.

You will collaborate with layout, verification, and silicon validation teams to deliver robust, production-ready designs, with a hybrid work model requiring 3 days onsite.