Senior Design Engineer - 5G & RTL Innovation (Hybrid)

AccelerComm Ltd; West (TX); Hybrid; USD 110,000 - 165,000; Full time

Benefits offered by this job

Bonus up to 20% of salary

Stock options

401K

Health/dental/optical insurance

Hybrid working

Job summary

AccelerComm Ltd. is seeking Design Engineers to work on cutting-edge wireless technology projects, developing IP, system and board solutions for 5G. The role emphasizes hands-on RTL design, verification, and collaboration with an elite team across a growing product portfolio.

We require 4+ years of relevant experience, with SystemVerilog, EDA tools, AXI interfacing and strong C/C++/Matlab prototyping skills. Hybrid work and competitive compensation offered in the United States.

Qualifications

• Degree qualified (or equivalent).
• 4+ years of experience in relevant field.
• Proficiency with EDA tools for simulation and synthesis (ModelSim, Quartus, Vivado, DC, Genus).
• AXI interfacing.
• Timing and hardware resource optimisation for high throughput data or signal processing applications.
• C/C++/Matlab prototyping for design and verification.
• Version control and peer review (Git).
• Documentation (Confluence).
• Time management (Jira).
• Desirable: maintenance of EDA tools; documenting innovations (publications/patents); automation (Jenkins); knowledge of communications signal processing algorithms; mobile communications systems; telecom/semiconductor industries.

Responsibilities

• Flexibly apply skills and expertise to enable team delivery of success at a project level.
• Collaborate with colleagues on the architecture, design, development, verification and documentation of our IP.
• Develop RTL implementations of electronics systems for communication, using SystemVerilog.
• Develop test benches for RTL implementations of electronics systems for communication, using SystemVerilog.

Skills

4+ years of experience in relevant fiel

SystemVerilog knowledge

C/C++/Matlab prototyping

Version control (Git)

Documentation (Confluence)

Time management (Jira)

AXI interfacing

Education

Degree qualified (or equivalent)

Tools

Mentor Graphics ModelSim

Altera Quartus

Xilinx Vivado

Synopsys DC

Cadence Genus

Job description

AccelerComm Ltd. is seeking Design Engineers to work on cutting-edge wireless technology projects, developing IP, system and board solutions for 5G. The role emphasizes hands-on RTL design, verification, and collaboration with an elite team across a growing product portfolio.

We require 4+ years of relevant experience, with SystemVerilog, EDA tools, AXI interfacing and strong C/C++/Matlab prototyping skills. Hybrid work and competitive compensation offered in the United States.