Senior CPU Verification Lead — High-Impact SoC & Equity

Google; Portland (OR); On-site; USD 240,000 - 333,000; Full time

Job summary

Google LLC is seeking a Senior Staff CPU Design Verification Lead to drive verification architectures and methodologies for complex ASIC/SoC designs. Lead test planning, testbench development, and coverage closure while architecting advanced environments using SystemVerilog and UVM to maximize test coverage.

Ideal candidates will have 15+ years in verification, experience leading teams for ARM/X86-ISA based processors, and strong knowledge of mobile processor micro-architecture and related

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 15 years of experience with verification methodologies and languages, such as UVM and SystemVerilog.
• Experience leading a functional verification team for ARM or X86 compliant processor-based products.
• Experience with functional verification and performance validation of modern mobile processors, micro-architecture, and related technologies.

Responsibilities

• Lead the definition of verification architectures and methodologies for complex ASIC and SoC designs.
• Drive the overall verification strategy, including test planning, testbench development, and coverage closure metrics.
• Architect advanced verification environments using SystemVerilog and UVM to ensure maximum test coverage.
• Define formal verification strategies to mathematically prove design correctness for critical hardware blocks.
• Establish emulation and post-silicon validation plans to accelerate system-level integration and debugging.

Skills

Verification leadership

Functional verification

Performance validation

Testbench development

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science

Master's or PhD preferred

Tools

UVM

SystemVerilog

Job description

Google LLC is seeking a Senior Staff CPU Design Verification Lead to drive verification architectures and methodologies for complex ASIC/SoC designs. Lead test planning, testbench development, and coverage closure while architecting advanced environments using SystemVerilog and UVM to maximize test coverage.

Ideal candidates will have 15+ years in verification, experience leading teams for ARM/X86-ISA based processors, and strong knowledge of mobile processor micro-architecture and related