Senior CPU Verification Engineer - SystemVerilog & C

Apple Inc.; Beaverton (OR); On-site; USD 140,000 - 190,000; Full time

Job summary

Apple Inc. in Beaverton, Oregon is seeking a CPU Design Verification Engineer to own verification of a specific functional area of a CPU design.

You will collaborate with architecture and RTL teams to verify correctness, develop test plans, and create tests in assembly, C, or vectors to ensure coverage across test plans. Responsibilities include building coverage monitors, developing checkers, and creating SystemVerilog or C-based transactors to verify the design.

Qualifications

• Minimum BS and 10+ years of relevant industry experience.
• Experience with CPU architecture.
• Experience with digital logic design, chip architecture, and microarchitecture.
• Programming experience in C/C++ or SystemVerilog.
• Experience with developing testplans/testbenches, C-based transactors, and writing/debugging tests.

Responsibilities

• Work closely with architecture and RTL designers on verifying the functional correctness of the design.
• Develop test plans and test environments.
• Develop tests in assembly, C, or vectors according to test plans.
• Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered.
• Develop checkers and SystemVerilog or C-base transactors to verify the design.

Skills

CPU architecture

Digital logic design

Chip microarchitecture

C/C++

SystemVerilog

Education

Bachelor of Science in Electrical Engineering

Bachelor of Science in Computer Engineering

Bachelor of Science in Computer Science

Tools

Testbenches

Job description

Apple Inc. in Beaverton, Oregon is seeking a CPU Design Verification Engineer to own verification of a specific functional area of a CPU design.

You will collaborate with architecture and RTL teams to verify correctness, develop test plans, and create tests in assembly, C, or vectors to ensure coverage across test plans. Responsibilities include building coverage monitors, developing checkers, and creating SystemVerilog or C-based transactors to verify the design.