Senior CPU Timing & Closure Engineer

Apple Inc.; Beaverton (OR); On-site; USD 130,000 - 160,000; Full time

Job summary

A leading technology company in Beaverton, Oregon, is seeking a CPU Design Timing Engineer to take responsibility for timing closure and collaborate with teams on timing changes. Candidates should have a minimum of a Bachelor's degree and 10 or more years of relevant experience, particularly in static timing analysis tools such as PrimeTime and knowledge of noise analysis, scripting, and variation modeling. Join this company that values diversity and equal opportunity.

Qualifications

• Minimum BS and 10+ years of relevant experience.
• Experience with static timing analysis tools such as PrimeTime or Tempus.
• Experience with timing analysis with multiple clock and power domains.

Responsibilities

• Work with the CAD team to develop the timing flow for the project.
• Collaborate with micro-architects and engineers to drive timing closure.

Skills

Static timing analysis tools (PrimeTime, Tempus)

TCL scripting

Perl or Python

Noise analysis

Variation modeling

SDC command usage

Education

Bachelor's degree

Job description

A leading technology company in Beaverton, Oregon, is seeking a CPU Design Timing Engineer to take responsibility for timing closure and collaborate with teams on timing changes. Candidates should have a minimum of a Bachelor's degree and 10 or more years of relevant experience, particularly in static timing analysis tools such as PrimeTime and knowledge of noise analysis, scripting, and variation modeling. Join this company that values diversity and equal opportunity.