Senior CPU SOC Methodology Architect

NVIDIA; Santa Clara (CA); On-site; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA seeks a Senior CPU Design Methodology Engineer in Santa Clara, CA to advance SOC design automation, RTL integration, and chip build/assembly. You will work with ASIC, Physical Design, CAD, Package Design, Software, DFT, and other teams to develop scalable methodologies for SOC creation.

Ideal candidates have 8+ years in chip design, strong Verilog/SystemVerilog skills, and proficiency in Perl/Python scripting. Equity and comprehensive benefits are offered; base salary varies by Level 4–5.

Qualifications

• Masters in Computer or Electrical Engineering or equivalent experience.
• 8+ years of chip design experience focusing on SOC integration and design automation.
• Excellent analytical and problem-solving skills.
• Experience in RTL design (Verilog), verification (UVM, SystemVerilog), SoC design/integration flow, and design automation.
• Strong coding skills in Perl, Python, or other scripting languages.
• Experience in synthesis and physical design is a plus.
• Good interpersonal skills.

Responsibilities

• Define and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner.
• Identify inefficiencies and improvement opportunities in the front-end chip implementation process and propose ideas to address them.
• Own front-end design quality checks and reviews to present the physical design team with high-quality RTL.

Skills

RTL design

Verification (UVM)

SystemVerilog

Design automation

Perl/Python scripting

Education

Master's degree in Computer or Electrical Engineering

Tools

Synthesis tools

Physical design tools

Job description

NVIDIA seeks a Senior CPU Design Methodology Engineer in Santa Clara, CA to advance SOC design automation, RTL integration, and chip build/assembly. You will work with ASIC, Physical Design, CAD, Package Design, Software, DFT, and other teams to develop scalable methodologies for SOC creation.

Ideal candidates have 8+ years in chip design, strong Verilog/SystemVerilog skills, and proficiency in Perl/Python scripting. Equity and comprehensive benefits are offered; base salary varies by Level 4–5.