Senior CPU Design Methodology & Automation Engineer

NVIDIA; Arizona; On-site; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Senior CPU Design Methodology Engineer in the United States. The role focuses on building scalable SOC methodologies and automation for front-end chip processes, interfacing with ASIC, Physical Design, CAD, and packaging teams.

You will drive RTL quality and automation across SOC flows, delivering optimized designs. The position requires a Master’s degree in Computer or Electrical Engineering (or equivalent) with 8+ years in chip design, strong Verilog/UVM/SystemVerilog

Qualifications

• Masters in Computer or Electrical Engineering or equivalent experience.
• 8+ years of chip design experience, specializing in SOC integration and design automation.
• Excellent analytical and problem-solving skills.
• Experience in RTL design (Verilog), verification (UVM, SystemVerilog), SOC design/integration flow, and design automation.
• Strong coding skills in Perl, Python, or other industry-standard scripting languages.
• Experience in synthesis and physical design is a plus.
• Good interpersonal skills.

Responsibilities

• Define and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner.
• Identify inefficiencies and improvement opportunities in the front-end chip implementation process and propose ideas to address them.
• Own front-end design quality checks and reviews to present the physical design team with high-quality RTL.

Skills

RTL design Verilog

UVM/SystemVerilog verification

SOC design/integration flow

Design automation

Perl/Python scripting

Education

Master's in Computer or Electrical Engineering

Tools

Synthesis tools

Physical design tools

Job description

NVIDIA is seeking a Senior CPU Design Methodology Engineer in the United States. The role focuses on building scalable SOC methodologies and automation for front-end chip processes, interfacing with ASIC, Physical Design, CAD, and packaging teams.

You will drive RTL quality and automation across SOC flows, delivering optimized designs. The position requires a Master’s degree in Computer or Electrical Engineering (or equivalent) with 8+ years in chip design, strong Verilog/UVM/SystemVerilog