Senior CPU Design Automation & Methodology Engineer

NVIDIA; Austin (TX); On-site; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits package

Job summary

NVIDIA is seeking a Senior CPU Design Methodology Engineer in Austin, TX to define scalable SOC methodologies and tools for front-end chip implementation. You will work with ASIC, Physical Design, CAD, and software teams to optimize RTL quality and automation.

You will build and risk-evaluate front-end workflows, improve efficiency, and contribute to high-quality RTL that enables the next generation of CPU technologies.

Qualifications

• Masters in Computer or Electrical Engineering or equivalent experience.
• 8+ years of chip design experience, specializing in SOC integration and design automation.
• Excellent analytical and problem-solving skills.
• Experience in RTL design (Verilog), verification (UVM, SystemVerilog), SoC design/integration flow, and design automation.
• Strong coding skills in Perl, Python, or other industry-standard scripting languages.

Responsibilities

• Define and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner.
• Identify inefficiencies and improvement opportunities in the front-end chip implementation process and propose ideas to address them.
• Own front-end design quality checks and reviews to present the physical design team with high-quality RTL.

Skills

Analytical thinking

Problem-solving

Interpersonal skills

Education

Master's in Electrical Engineering or Computer Science

Tools

Verilog RTL

UVM

SystemVerilog

Design automation

Synthesis

Physical design

Perl

Python

Job description

NVIDIA is seeking a Senior CPU Design Methodology Engineer in Austin, TX to define scalable SOC methodologies and tools for front-end chip implementation. You will work with ASIC, Physical Design, CAD, and software teams to optimize RTL quality and automation.

You will build and risk-evaluate front-end workflows, improve efficiency, and contribute to high-quality RTL that enables the next generation of CPU technologies.