Senior CPU Design Methodology Engineer | Equity

NVIDIA Corporation; Santa Clara, Northern (CA, KY); Hybrid; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Generous benefits

Job summary

NVIDIA Corporation in Santa Clara, CA is seeking a Senior CPU Design Methodology Engineer to lead system-level methodologies for SOC creation and front-end design quality. You will help define scalable processes, automate RTL integration, and collaborate with ASIC, Physical Design, CAD, and Software teams.

The role requires a Masters in Computer or Electrical Engineering and 8+ years in chip design with SOC integration, plus strong scripting skills in Perl or Python.

Qualifications

• Masters in Computer or Electrical Engineering or equivalent experience.
• 8+ years of experience in chip design, specializing in SOC integration and design automation.
• Excellent analytical and problem-solving skills.
• Experience in RTL design (Verilog), verification (UVM, System Verilog), System-On-Chip design/integration flow, and design automation.
• Strong coding skills in Perl, Python, or other industry-standard scripting languages.
• Experience in synthesis and physical design is a plus.
• Good interpersonal skills.

Responsibilities

• Define and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner
• Identify inefficiencies and improvement opportunities in the front-end chip implementation process and propose ideas to address them
• Own front-end design quality checks and reviews to present the physical design team with high-quality RTL

Skills

RTL design Verilog

UVM SystemVerilog

SOC integration

Design automation

Perl

Python

Analytical thinking

Education

Master's degree in Computer or Electrical Engineering

Job description

NVIDIA Corporation in Santa Clara, CA is seeking a Senior CPU Design Methodology Engineer to lead system-level methodologies for SOC creation and front-end design quality. You will help define scalable processes, automate RTL integration, and collaborate with ASIC, Physical Design, CAD, and Software teams.

The role requires a Masters in Computer or Electrical Engineering and 8+ years in chip design with SOC integration, plus strong scripting skills in Perl or Python.