Senior CPU Physical Design & Tape-Out Lead

NUVACORE; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As a CPU Physical Design Integration engineer, you will lead end-to-end integration, physical verification and final tape-out signoff checks, collaborating with packaging, CAD, RTL and foundry teams.

The role demands deep expertise in PV, PERC, ESD, bump and RDL, and a track record of multiple SOC tape-outs on modern nodes.

Qualifications

• BS or MS in electrical/computer engineering is required.
• 12+ years of experience in CPU PD integration for lead roles; or 5+ years for individual contributors.
• Deep expertise in Physical Verification, PERC, ESD, Bump & RDL.
• Expertise in CPU blocks lego planning based on technology rules.
• Experience with end-to-end physical design implementation and signoff.

Responsibilities

• Lead and/or participate in floorplan development and area optimization.
• Own end-to-end Physical Design Integration methodology and execution.
• Drive PV, PERC, and ESD signoff efforts.
• Own bump and RDL design with the packaging team.
• Manage analog interfaces, signal construction and implementation.
• Interface with foundry and technology teams as needed.
• Develop Tools, Flow and Methodology (TFM) with the CAD team across domains.
• Collaborate with CPU and subsystem owners, CAD/RTL teams as needed.

Skills

Strong communication

CPU physical design

Physical verification

PERC

ESD

Bump & RDL

Education

BS or MS in Electrical/Computer Engineering

Tools

Siemens EDA

Synopsys

Cadence

Job description

Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As a CPU Physical Design Integration engineer, you will lead end-to-end integration, physical verification and final tape-out signoff checks, collaborating with packaging, CAD, RTL and foundry teams.

The role demands deep expertise in PV, PERC, ESD, bump and RDL, and a track record of multiple SOC tape-outs on modern nodes.