Senior CPU Physical Design Integration & Signoff Architect

NUVACORE; Austin (TX); On-site; USD 150,000 - 210,000; Full time

Job summary

Nuvacore is seeking a CPU Physical Design Integration Engineer to drive end-to-end PD integration, verification, and tape-out signoff for next-gen CPUs.

Role involves floorplanning, area optimization, PV/PERC/ESD signoff, bump/RDL design, analog interfaces, and close collaboration with packaging, CAD, RTL, and foundry teams. Requires 5+ years (IC) or 12+ years (Lead) in PD integration and strong scripting skills.

Qualifications

• BS or MS in CPU physical design integration.
• 12+ years of experience for Lead roles or 5+ years for IC roles in CPU PD integration.
• Experience with multiple tape-outs of SoCs in latest tech nodes.
• Deep expertise in PV, PERC, ESD, Bump & RDL; design closure across signoff domains.

Responsibilities

• Lead and/or participate in floorplan development and area optimization.
• Own end-to-end Physical Design Integration methodology and execution.
• Drive PV, PERC, and ESD signoff efforts; own bump and RDL design with packaging team.
• Collaborate with CAD, RTL, and subsystem teams; interface with foundry and tech teams.

Skills

CPU PD integration

Physical verification

PERC/ESD signoff

Bump & RDL design

Signoff flow

Python/Perl/Tcl scripting

Tape-out experience

EDA tools (Siemens/Synopsys/Cadence)

End-to-end PD implementation

Communication skills

Education

BS or MS in CPU physical design integration

Tools

Siemens

Synopsys

Cadence

Job description

Nuvacore is seeking a CPU Physical Design Integration Engineer to drive end-to-end PD integration, verification, and tape-out signoff for next-gen CPUs.

Role involves floorplanning, area optimization, PV/PERC/ESD signoff, bump/RDL design, analog interfaces, and close collaboration with packaging, CAD, RTL, and foundry teams. Requires 5+ years (IC) or 12+ years (Lead) in PD integration and strong scripting skills.