CPU Physical Design Integration

NUVACORE; Austin (TX); On-site; USD 150,000 - 210,000; Full time

Job summary

Nuvacore is seeking a CPU Physical Design Integration Engineer to drive end-to-end PD integration, verification, and tape-out signoff for next-gen CPUs.

Role involves floorplanning, area optimization, PV/PERC/ESD signoff, bump/RDL design, analog interfaces, and close collaboration with packaging, CAD, RTL, and foundry teams. Requires 5+ years (IC) or 12+ years (Lead) in PD integration and strong scripting skills.

Qualifications

• BS or MS in CPU physical design integration.
• 12+ years of experience for Lead roles or 5+ years for IC roles in CPU PD integration.
• Experience with multiple tape-outs of SoCs in latest tech nodes.
• Deep expertise in PV, PERC, ESD, Bump & RDL; design closure across signoff domains.

Responsibilities

• Lead and/or participate in floorplan development and area optimization.
• Own end-to-end Physical Design Integration methodology and execution.
• Drive PV, PERC, and ESD signoff efforts; own bump and RDL design with packaging team.
• Collaborate with CAD, RTL, and subsystem teams; interface with foundry and tech teams.

Skills

CPU PD integration

Physical verification

PERC/ESD signoff

Bump & RDL design

Signoff flow

Python/Perl/Tcl scripting

Tape-out experience

EDA tools (Siemens/Synopsys/Cadence)

End-to-end PD implementation

Communication skills

Education

BS or MS in CPU physical design integration

Tools

Siemens

Synopsys

Cadence

Job description

Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As a member of our CPU physical design integration team, you'll drive end-to-end integration, physical verification and final tape-out signoff checks.

THE ROLE

As a CPU Physical Design (PD) Engineer for Integration you will participate in the following :

• Lead and/or participate in overall floorplan development and drive area optimization
• Own and develop the end-to-end Physical Design Integration methodology and execution.
• Drive and participate in efforts for Physical Verification (PV), PERC, and ESD signoff
• Own bump and RDL design in close collaboration with the internal packaging team.
• Own the complete analog interfaces, and custom signal construction and implementation.
• Interface directly with foundry and technology teams as required.
• Partner with the internal CAD team to develop and maintain the Tools, Flow and Methodology (TFM) across all relevant design domains.
• Collaborate with CPU and subsystem unit owners, custom circuit designers, CAD engineers, and RTL teams as needed.

Minimum Qualifications

• Hold a BS or MS degree with 12+ years of experience (for Lead roles) or 5+ years of experience (for Individual Contributor roles) in CPU physical design integration
• Experience in multiple tape-outs of SoCs in the latest technology nodes relevant for CPUs.
• Deep expertise in Physical Verification, PERC, ESD, Bump & RDL.
• Expertise in CPU blocks lego planning based on technology rules.
• Experience in Physical design integration methodologies and Signoff process.
• Proficiency with Siemens, Synopsys or Cadence EDA tools for Physical Design.
• Comprehensive understanding of end-to-end physical design implementation and design closure across all signoff domains.
• Strong communication skills with the ability to build processes and infrastructure from the ground up.

Requirements — Preferred

• Experience with PNR (Place and Route) & owning blocks.
• Proficiency in scripting languages including Python, Perl, and/or TCL for design automation and flow development.

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.