CPU Full-chip Physical Integration Engineer

Apple Inc.; Beaverton (OR); On-site; USD 120,000 - 150,000; Full time

Job summary

Apple Inc. is seeking a CPU Full-chip Physical Integration Engineer in Beaverton, Oregon. The successful candidate will participate in the physical design and integration of high-performance processors.

Responsibilities include owning chip-level place and route, verification, and collaborating with teams throughout the design cycle. Candidates should have a Bachelor's degree and over 10 years of relevant industry experience.

Join Apple in fostering a diverse workplace that welcomes everyone.

Qualifications

• Minimum BS and 10+ years of relevant industry experience.
• Experience with scripting in Perl or TCL.
• Solid knowledge of Low Power Design and Physical Verification.

Responsibilities

• Participating in the physical design and integration of processors.
• Own chip level place and route (PnR) and final CPU layout verification.
• Work with implementation teams to drive closure for tapeout.

Skills

Physical Design

Scripting (Perl or TCL)

Problem Solving

Team Collaboration

Education

Bachelor's degree

Tools

Conformal LP

LEC

RedHawk

Calibre

Job description

CPU Full-chip Physical Integration Engineer

Apple’s Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation.

Description

• Participating in the physical design, integration, and verification of high performance, low power processor development.
• Full chip floorplan, area optimizations, block partitioning and pin placements.
• Own chip level place and route (PnR), final CPU layout database construction and verification (PDV).
• Develop and validate Power Grid, including routability analysis.
• Drive custom layout integration, block and full-chip level EM/IR, electrical verification/analysis as well as formal verification.
• Work with the implementation/CAD teams during the entire chip design cycle to drive signoff closure for tapeout.
• Work with the SOC team to meet IP technical and delivery requirements.
• Participate in establishing CAD and physical design methodologies and flow development for chip integration and analysis.
• Scripting to automate tasks and improve debug efficiency.

Minimum Qualifications

• Minimum BS and 10+ years of relevant industry experience
• Experience with scripting in Perl or TCL

Preferred Qualifications

• Knowledge of industrial standards and practices in Physical Design, including Floorplanning, Partitioning, Budgeting, Place and Route and Physical Verification
• Experience in developing and implementing Power Grid and Clock specifications
• Solid knowledge of Low Power Design, Physical Construction, Integration, EMIR (Drop/Noise), SIGEM Analysis, Formal Verification, Physical PDV, DRC/LVS Verification, and DFM
• Solid understanding of verification tools such as Conformal LP, LEC, RedHawk, Calibre
• Solid understanding of CMOS circuit design. Layout design background is a plus
• Working knowledge of Extraction and STA methodology and tools
• Working knowledge of Computer Architecture
• Ability to work well in a team, being an excellent problem solver, and self motivated

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.