Senior CPU Microarchitecture & RTL Design Engineer

Qualcomm Innovation Center, Inc.; Austin (TX); On-site; USD 217,000 - 325,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking talented engineers for CPU RTL development focused on high performance, low power devices.

As a CPU Micro-architecture and RTL Design Engineer, you will collaborate with chip architects to define micro-architecture and participate early in product life-cycle. Key work includes architecture exploration, RTL ownership, verification, and delivering design implementations across timing, power, and area targets.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 8+ years of relevant experience.
• 8+ years of Hardware/Software or related work experience.
• Experience in CPU RTL/architecture domains is a plus.

Responsibilities

• Performance exploration with CPU modeling team.
• Develop and specify CPU microarchitecture from high-level exploration to detailed specs.
• RTL ownership to meet power, performance, area, timing goals.
• Support functional verification strategy.
• Support performance verification to ensure RTL meets goals.
• Collaborate across multi-functional teams to implement and validate physical design aspects.

Skills

Microprocessor architecture

Verilog

VHDL

Scripting (Perl/Python)

Low power microarchitecture

High performance CPU design

Education

Bachelor's degree in Electrical/Computer Engineering or CS

Master's degree in Electrical/Computer Engineering or CS

PhD in Electrical/Computer Engineering or CS

Tools

Simulators

Waveform debugging tools

Job description

Qualcomm Technologies, Inc. is seeking talented engineers for CPU RTL development focused on high performance, low power devices.

As a CPU Micro-architecture and RTL Design Engineer, you will collaborate with chip architects to define micro-architecture and participate early in product life-cycle. Key work includes architecture exploration, RTL ownership, verification, and delivering design implementations across timing, power, and area targets.