Senior CPU Microarchitecture & Logic Design Engineer

AheadComputing, Inc.; Portland (OR); On-site; USD 120,000 - 190,000; Full time

Job summary

AheadComputing, Inc. is seeking a Senior CPU Design Engineer to design and implement high-performance execution units, optimizing for power, performance, and area (PPA). You will shape microarchitecture, develop RTL, and validate designs across cross-functional teams.

You will collaborate with verification and physical design teams to ensure timing, area and reliability targets are met, and you will prototype and validate core and subsystem RTL across simulations and silicon.

Qualifications

• Bachelor's degree with 4+ years of related experience, or higher degree with fewer years.
• Strong understanding of microprocessor architecture and microarchitecture.
• Experience with SystemVerilog RTL development and front-end tools.
• Proficient in C/C++ and Python; strong analytical skills.

Responsibilities

• Define, develop, and refine microarchitecture specifications for complex CPU subsystems.
• Design and implement RTL to meet target power, performance, area, and timing goals.
• Collaborate with verification to establish validation strategies for new designs.
• Support test bench development and assist validation engineers in testing and debugging RTL.
• Work with physical design teams to meet timing, area, and power requirements.

Skills

Microprocessor architecture

PPA optimization

Problem solving

Cross‑functional collaboration

RTL debugging

Education

Bachelor's degree in Electrical/Computer Engineering, Computer Science, or related field

Master's degree in Electrical/Computer Engineering, Computer Science, or related field

PhD in a related field

Tools

SystemVerilog RTL development

Verilog simulators

Logic synthesis

Place-and-route tools

C/C++

Python

Job description

We are seeking a Senior CPU Design Engineer to join our team. In this role, you will be responsible for designing and implementing high-performance execution units in CPU, optimizing for power, performance, and area (PPA). You will work closely with cross-functional teams to refine microarchitecture, develop RTL, and validate designs. This is an opportunity to work on challenging projects and play a key role in defining execution unit architecture for next-generation CPU designs.

Responsibilities

• Define, develop, and refine microarchitecture specifications for complex CPU subsystems.
• Design and implement RTL to achieve targeted power, performance, area, and timing goals.
• Collaborate closely with the verification team to establish effective validation strategies for new designs.
• Support test bench development and assist validation engineers in testing and debugging core and subsystem-level RTL in simulation, prototyping platforms, and silicon.
• Work with physical design teams to ensure that the design meets timing, area, reliability, testability, and power requirements.

Minimum Qualifications:

• Bachelor's degree in Electrical/Computer Engineering, Computer Science, or a related field with 4+ years of experience; OR a Master's degree with 3+ years of experience; OR a PhD with 1+ years of experience.
• Strong understanding of microprocessor architecture and microarchitecture.
• Proficiency in applying trade-off and optimization techniques for performance, power, and area (PPA) in high-frequency design.
• Experience with SystemVerilog RTL development.
• Hands-on experience with front-end tools such as Verilog simulators, waveform viewers, linting tools, logic synthesis, and place-and-route.
• Programming skills in C/C++ and Python.
• Strong problem-solving skills and an analytical mindset.

Preferred Qualifications:

• Experience with one or more of the following areas:
• High performance branch prediction, instruction fetch, instruction decode, instruction caches
• Coherency protocols, memory consistency, L1/L2 caches, and TLBs design
• Out-of-order execution, including allocation, renaming, scheduling, and retirement.
• ALU, floating-point, and vector operations.