Principal Engineer, Architecture & Performance Research for Data Center and Agentic AI CPU

Engg; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Engg in San Jose is seeking a Principal Engineer for Architecture & Performance Research focused on data center and agentic AI CPU. You will lead microarchitectural vision for next‑gen CPU cores (RISC‑V, ARM, x86), drive performance analyses with simulators and RTL, and guide trade‑offs from workload characterization to silicon validation.

Based in San Jose with daily onsite presence, you will mentor engineers, publish patents, and push AI‑driven design methodologies to advance future CPUs and

Qualifications

• Master’s degree in Computer Engineering, Computer Science, or related field; 18+ years of experience or PhD with 15+ years of experience.
• Extensive experience in CPU microarchitecture, architecture research, or performance engineering.
• Proven ability to drive architectural direction and evaluate high-performance CPU architectures (RISC-V, ARM, x86).
• Strong quantitative analysis, modeling, and ability to translate workload insights into design decisions.
• Hands-on experience with simulators and RTL; capable of guiding RTL to silicon validation.
• Proficient in C/C++ and Python; developing tools for performance analysis.

Responsibilities

• Define the application-specialization direction for next-generation CPU cores (agentic AI, memory-centric architectures).
• Lead end-to-end performance analysis using architectural simulators and RTL.
• Translate workload characterization into architectural requirements and long-term design direction.
• Drive alignment from architecture to RTL and silicon with design teams.
• Mentor Senior and Staff engineers across multiple projects.
• Contribute to patents and publications.

Skills

CPU microarchitecture

Architecture research

Performance engineering

Quantitative analysis & modeling

C/C++ programming

Python programming

RTL implementation

Gem5 simulation

Education

Master’s degree in Computer Engineering/Computer Science

PhD in related field

Tools

Gem5

Job description

Advancing the World’s Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

Principal Engineer , Architecture & Performance Research Engineer for Data Center and Agentic AI CPU

What You’ll Do

Architecture Research Lab is focused on researching next-generation CPU (RISC-V) microarchitecture and performance for emerging computing workloads. We explore new architectural ideas, evaluate their performance potential, and rapidly turn promising concepts into working designs that can be validated on real silicon. Our research is driven by emerging opportunities in data center and agentic AI workloads, where we investigate how CPU architecture can evolve to meet new performance and efficiency requirements. We also explore CPU‑memory co‑design from the CPU perspective, in alignment with the broader shift toward memory‑centric architectures. A distinctive aspect of our team is the way we approach architecture research. We develop and apply AI‑driven methodologies to accelerate architectural exploration, broaden the design space we can investigate, and quickly iterate from ideas to implementation and silicon validation. Rather than simply following established design flows, we continuously seek new ways to explore, evaluate, and realize CPU architectures. The role offers an opportunity to work across the full spectrum of architecture research—from workload and performance analysis, microarchitectural innovation, and architectural modeling to implementation and silicon validation—while helping shape new methodologies for how future CPUs are designed.

Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy Job ID: 43044

• Define the application‑specialization direction for next‑generation CPU cores, including agentic AI and memory‑centric architectures, and lead the overall microarchitectural vision
• Lead end-to-end performance analysis using architectural simulators and RTL, guiding key architectural trade-offs and decisions
• Translate workload characterization and performance insights into architectural requirements and long‑term design direction
• Drive architecture-to‑implementation alignment with design teams, ensuring architectural intent is carried through RTL and silicon
• Mentor Senior and Staff engineers and provide technical leadership across multiple projects and architectural domains
• Drive research and technical contributions leading to patents and publications

What You Bring

• Master’s degree in Computer Engineering, Computer Science, or a related field with 18+ years of relevant experience, or PhD with 15+ years of relevant experience
• 5+ years of experience in CPU microarchitecture, architecture research, or performance engineering, with a demonstrated track record of driving architectural direction
• Extensive experience designing and evaluating high-performance CPU architectures, including RISC‑V, ARM, or x86 cores; experience with GPU/NPU vector or accelerator architectures is also relevant
• Proven ability to use quantitative performance analysis and modeling to identify architectural opportunities, evaluate system-level trade-offs, and influence major microarchitectural decisions
• Deep expertise in at least one major microarchitectural domain, with the ability to drive architectural direction and technical decisions in that area: Front-end: Branch prediction, fetch/decode, instruction delivery, and decoupled front-end architectures Mid-end: Out-of-order execution, scheduling, RVV/SIMD, vector execution, or matrix/tensor acceleration Back-end: Load/store units, MSHRs, cache and memory systems, prefetching, or irregular memory access optimization
• Hands-on experience building, extending, and applying architectural simulators and performance models, such as gem5, to guide architecture decisions
• Strong programming skills in C/C++ and Python, with experience developing tools and automation for performance analysis and architectural exploration
• Demonstrated ability to take architectural concepts from research and modeling through RTL implementation and silicon validation

Preferred Qualifications

• Experience defining or influencing CPU architecture for emerging workloads, particularly AI/ML, agentic AI, or data center applications
• Experience with AI-driven architecture and design methodologies, including AI-assisted architecture exploration, high-level design, or RTL generation
• Strong perspective on m