Senior CPU Core RTL Engineer — High-Performance Pipelines

Advanced Micro Devices, Inc; Austin (TX); On-site; USD 140,000 - 190,000; Full time

Job summary

AMD in Austin is seeking a CPU Core RTL Design Engineer to design and optimize next-generation processor cores. You will work with architecture, performance, verification, and physical design partners to develop core pipeline logic and microarchitecture features, impacting performance, power, and scalability.

You should have strong Verilog/SystemVerilog RTL experience and deep CPU architecture knowledge, with a collaborative mindset to drive complex pre- and post-silicon work.

Qualifications

• Experience with Verilog/SystemVerilog RTL development in CPU, SoC, or ASIC environments.
• Strong understanding of modern CPU architecture, esp. out-of-order cores.
• Expertise in logic design and high-speed processor pipeline development.

Responsibilities

• Design and implement RTL for CPU core pipeline components and related logic.
• Contribute to microarchitecture definition for next-generation processor cores.
• Collaborate with architecture, verification, and performance teams to deliver optimized designs.
• Analyze and improve performance, power, and timing characteristics.
• Support design verification, synthesis, timing closure, and physical design efforts.
• Debug and resolve pre-silicon and post-silicon issues.
• Partner with cross-functional teams to align on design trade-offs and execution.
• Contribute to scalable RTL methodologies, libraries, and best practices.

Skills

Verilog/SystemVerilog RTL

CPU architecture

Pipeline design

Power optimization

Synthesis & PnR

Debug & verification

Education

Bachelor’s, Master’s, or PhD in Electrical Engineering or Computer Engineering

Tools

Python scripting

Tcl scripting

Job description

AMD in Austin is seeking a CPU Core RTL Design Engineer to design and optimize next-generation processor cores. You will work with architecture, performance, verification, and physical design partners to develop core pipeline logic and microarchitecture features, impacting performance, power, and scalability.

You should have strong Verilog/SystemVerilog RTL experience and deep CPU architecture knowledge, with a collaborative mindset to drive complex pre- and post-silicon work.