Senior CPU Core RTL Engineer: High-Performance Pipelines

Hardware FYI; Austin (TX); On-site; USD 140,000 - 240,000; Full time

Job summary

AMD is seeking a CPU Core RTL Design Engineer in Austin to design and optimize high-performance processor cores. You will work with architecture, performance, verification, and physical design teams to deliver efficient RTL and microarchitectural features.

You will contribute to core pipeline logic, participate in design trade-offs, and help ensure timing, power, and scalability goals are met through the full product lifecycle of client/server/AI platforms.

Qualifications

• Experience with Verilog/SystemVerilog RTL in CPU/SoC/ASIC environments
• Strong understanding of modern CPU architecture, especially out-of-order cores
• Expertise in high-speed processor pipeline design
• Knowledge of load/store, cache hierarchy, address translation/TLB, prefetch, branch prediction or similar core subsystems
• Familiarity with power-efficient design techniques, timing and power optimization
• Experience with synthesis, place-and-route, and timing closure
• Experience debugging and optimizing designs with performance and verification teams
• Exposure to full product lifecycle from architecture to post-silicon debugging
• Familiarity with physical design, scripting (e.g., Python, Tcl) and DFT concepts

Responsibilities

• Design and implement RTL for CPU core pipeline components and related logic
• Contribute to microarchitecture definition for next-generation processor cores
• Collaborate with architecture, verification, and performance teams to deliver optimized designs
• Analyze and improve performance, power, and timing characteristics
• Support design verification, synthesis, timing closure, and physical design efforts
• Debug and resolve pre-silicon and post-silicon issues
• Partner with cross-functional teams to align on design trade-offs and execution
• Contribute to scalable RTL methodologies, libraries, and best practices

Skills

Verilog/SystemVerilog

CPU architecture

Logic design

RTL pipeline

Synthesis & P&R

Performance optimization

Debugging hardware

Python scripting

DFT concepts

Education

Bachelor’s/Master’s/PhD in Electrical or Computer Engineering

Job description

AMD is seeking a CPU Core RTL Design Engineer in Austin to design and optimize high-performance processor cores. You will work with architecture, performance, verification, and physical design teams to deliver efficient RTL and microarchitectural features.

You will contribute to core pipeline logic, participate in design trade-offs, and help ensure timing, power, and scalability goals are met through the full product lifecycle of client/server/AI platforms.