Senior CPU Core RTL Design Architect

Hardware FYI; Fort Collins (CO); On-site; USD 140,000 - 210,000; Full time

Job summary

AMD is seeking an experienced CPU Core RTL Design Engineer to design and optimize next-generation processor cores. You will work with architecture, verification, and performance teams to deliver high-performance RTL, focusing on core pipeline logic and microarchitecture features.

The role emphasizes collaboration across teams to balance performance, power, and timing while addressing pre-silicon and post-silicon challenges in a fast-changing field.

Qualifications

• Experience with Verilog/SystemVerilog RTL development in CPU, SoC, or ASIC environments.
• Strong understanding of modern CPU architecture, especially out-of-order cores.
• Expertise in logic design and high-speed processor pipeline development.
• Familiarity with synthesis, place-and-route, and timing closure.

Responsibilities

• Design and implement RTL for CPU core pipeline components and related logic.
• Contribute to microarchitecture definition for next-generation processor cores.
• Collaborate with architecture, verification, and performance teams to deliver optimized designs.
• Analyze and improve performance, power, and timing characteristics.
• Support design verification, synthesis, timing closure, and physical design efforts.
• Debug and resolve pre-silicon and post-silicon issues.
• Partner with cross-functional teams to align on design trade-offs and execution.
• Contribute to scalable RTL methodologies, libraries, and best practices.

Skills

Verilog/SystemVerilog RTL

CPU architecture

Logic design

Processor pipeline development

Python/Tcl scripting

Education

Electrical/Computer Engineering degree

Tools

Synthesis tools

Place-and-Route

DFT concepts

Job description

AMD is seeking an experienced CPU Core RTL Design Engineer to design and optimize next-generation processor cores. You will work with architecture, verification, and performance teams to deliver high-performance RTL, focusing on core pipeline logic and microarchitecture features.

The role emphasizes collaboration across teams to balance performance, power, and timing while addressing pre-silicon and post-silicon challenges in a fast-changing field.