Senior Design Lead, CPU Cache Subsystem

Google Inc.; Austin, Mountain View (TX, CA); On-site; USD 240,000 - 333,000; Full time

Job summary

Google Inc. is seeking a senior CPU design lead to own frontend design for advanced CPU subsystems.

You will guide RTL development, align micro-architecture with SOC targets, and work across architecture, software, verification, power, DFT and physical teams to meet project milestones. You will drive decisions on complexity, performance, power and area while mentoring a team to deliver high-quality RTL on schedule.

Qualifications

• Bachelors in Electrical Engineering, Computer Science or equivalent is required.
• 15 years of CPU design experience including load-store unit logic and caches.
• Proven leadership of teams for modern processor subsystems with high speed, low power design.
• Experience with front-end quality checks (e.g., Lint, CDC/RDC).

Responsibilities

• Lead and manage a front-end design team for CPU subsystems.
• Define micro-architecture and schedule RTL delivery for target SOCs.
• Collaborate with architecture, software, verification, power, DFT, and physical design teams.
• Evaluate design options considering complexity, performance, power and area.
• Focus on load-store-unit and cache subsystem design and optimizations.

Skills

Outcome ownership

Decision making

Stakeholder influence

Frontend design leadership

RTL/CPU design knowledge

Education

Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience

Tools

RTL design tools

CPU/SoC design tooling

Job description

Google Inc. is seeking a senior CPU design lead to own frontend design for advanced CPU subsystems.

You will guide RTL development, align micro-architecture with SOC targets, and work across architecture, software, verification, power, DFT and physical teams to meet project milestones. You will drive decisions on complexity, performance, power and area while mentoring a team to deliver high-quality RTL on schedule.