Senior CPU Cache Subsystem Design Lead

Google; Portland (OR); On-site; USD 240,000 - 333,000; Full time

Benefits offered by this job

Equity

Job summary

Google’s CPU hardware team in the United States is seeking a senior design lead to drive CPU subsystems from specification to productization, including SOC integration. You will mentor a front-end design group and coordinate with architecture, software, verification, power, DFT, and physical design teams to deliver high-quality RTL on schedule.

You will evaluate micro-architecture options, balance performance, power and area, and guide teams toward optimal design choices with a focus on

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 15 years of experience in CPU design, including load-store unit logic/RTL and L2/L3 private/shared caches including micro-architecture definition and PPA processing.
• Experience leading and managing teams for modern processor subsystems with high speed, lower power design.
• Experience with front-end quality checks (e.g., Lint, CDC/RDC).

Responsibilities

• Lead and manage a team of design engineers working on CPU functional units, emphasizing on micro-architecture and RTL design for the next generation CPU subsystem.
• Review/propose performance enhancing micro-architecture features, and work with Software, Architect and Performance teams for trade-off studies. Communicate the pros and cons of micro-architecture enhancements.
• Deliver with plans on achieving project milestones and goals, towards a design that meets production quality on schedule.
• Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals.
• Focus on load-store-unit and cache subsystem design and optimizations with other parts of CPU to deliver best Performance, Power, Area (PPA).

Job description

Google’s CPU hardware team in the United States is seeking a senior design lead to drive CPU subsystems from specification to productization, including SOC integration. You will mentor a front-end design group and coordinate with architecture, software, verification, power, DFT, and physical design teams to deliver high-quality RTL on schedule.

You will evaluate micro-architecture options, balance performance, power and area, and guide teams toward optimal design choices with a focus on