Senior CPU Cache & Subsystem Design Lead

Google; United States; On-site; USD 240,000 - 333,000; Full time

Benefits offered by this job

Bonus target 25%

Equity

Benefits

Job summary

Google is seeking a Senior Design Manager for the CPU Cache Subsystem to own and deliver advanced CPU subsystems. You will drive front-end RTL, define micro-architecture, and coordinate with architecture, software, and verification teams to hit milestones and quality targets.

You will mentor a design team, evaluate trade-offs across performance, power and area, and push innovative solutions for next-generation SoCs powering Google products.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 15 years of experience in CPU design, including load-store unit logic/RTL and L2/L3 private/shared caches.
• Experience leading and managing teams for modern processor subsystems with high speed, lower power design.
• Experience with front-end quality checks (e.g., Lint, CDC/RDC).

Responsibilities

• Lead and manage a front-end design team, collaborating with architecture, software, verification, power, DFT, physical design.
• Define micro-architecture and schedule RTL delivery to meet project goals.
• Evaluate design options considering complexity, performance, power and area.
• Work with verification and physical design teams to meet frequency, power, and area goals.
• Focus on load-store-unit and cache subsystem design to optimize PPA.

Skills

CPU design

RTL design

micro-architecture

L2/L3 caches

team leadership

front-end quality checks

Education

Bachelor's degree in Electrical Engineering or Computer Science

Tools

ARM ISA

mobile CPU subsystems

SOC integration

Job description

Google is seeking a Senior Design Manager for the CPU Cache Subsystem to own and deliver advanced CPU subsystems. You will drive front-end RTL, define micro-architecture, and coordinate with architecture, software, and verification teams to hit milestones and quality targets.

You will mentor a design team, evaluate trade-offs across performance, power and area, and push innovative solutions for next-generation SoCs powering Google products.