Senior CPU Architect: AI-Driven Performance & Architecture

Conductor; San Jose (CA); On-site; USD 138,000 - 206,000; Full time

Job summary

Conductor in San Jose, CA, seeks a Senior CPU Architecture & Performance Engineer to advance research for next‑generation data‑center CPUs and agentic AI workloads. You will drive microarchitectural modeling, performance analysis, and collaborate with RTL teams from modeling to silicon validation.

The role offers ownership across front‑end to back‑end optimizations, opportunities to publish patents, and work with AI‑driven design methods in a collaborative, inclusive environment.

Qualifications

• Master’s with Computer Architecture, Computer Engineering, or a related field.
• 3+ years of experience or PhD in Computer Architecture, Computer Engineering, or a related field
• 1+ years of experience in CPU microarchitecture or performance engineering
• Strong understanding of out-of-order execution, branch prediction, pipelines, speculation, and cache/memory systems
• Hands-on experience with architectural simulators such as gem5
• Proficiency in C/C++ and Python

Responsibilities

• Collaborate with Staff and Principal Engineers, owning a specific microarchitectural domain from idea proposal through implementation and validation
• Participate in design implementation and validation using AI-driven design methodologies
• Run architectural simulations and performance models, and analyze results such as IPC, CPI stacks, latency, and throughput
• Identify performance bottlenecks and optimization opportunities across the front-end, mid-end, and back-end
• Characterize workloads and benchmarks to understand performance behavior and architectural opportunities
• Develop scripts and tools to automate and accelerate performance analysis and architectural exploration
• Contribute to patents and technical publications based on novel architectural research

Skills

gem5

C/C++

Python

CPU microarchitecture

Performance engineering

Education

Master's in Computer Architecture / Computer Engineering

PhD in related field

Job description

Conductor in San Jose, CA, seeks a Senior CPU Architecture & Performance Engineer to advance research for next‑generation data‑center CPUs and agentic AI workloads. You will drive microarchitectural modeling, performance analysis, and collaborate with RTL teams from modeling to silicon validation.

The role offers ownership across front‑end to back‑end optimizations, opportunities to publish patents, and work with AI‑driven design methods in a collaborative, inclusive environment.