Staff CPU Architect: Data Center & Agentic AI Performance

Conductor; San Jose (CA); On-site; USD 163,000 - 253,000; Full time

Benefits offered by this job

Paid time off

Job summary

Samsung Semiconductor in San Jose, CA, seeks a Staff Engineer to lead architecture and performance research for next‑gen data center CPUs and agentic AI workloads. You’ll translate ideas into models and validate them from simulation to silicon, collaborating with RTL teams and researchers.

Ideal candidates: 8+ years in CPU microarchitecture or a PhD with 5+ years, strong C/C++ and Python, and experience with gem5 or similar simulators. You will shape architecture strategy and publish findings.

Qualifications

• Master’s degree in Computer Engineering/CS with 8+ years of experience
• PhD with 5+ years of relevant experience
• Strong understanding of CPU microarchitecture and performance engineering

Responsibilities

• Propose new architecture ideas and own one or more microarchitectural domains.
• Use AI-driven design methodologies to rapidly implement architectural ideas and validate them on real silicon.
• Build, extend, and validate performance models and architectural simulators.
• Perform CPI/IPC analysis and identify root causes of performance bottlenecks.
• Evaluate microarchitectural features and optimizations using trace-driven, analytical, and cycle-accurate models.
• Characterize workloads and benchmarks, including SPEC, server, client, AI/ML, agentic AI, and internal traces.
• Translate performance analysis and modeling results into architectural direction and design decisions.
• Drive research leading to patents and technical publications

Skills

Out-of-order execution

Branch prediction

Pipelines

Cache/memory systems

C/C++

Python

Performance modeling

Education

Master’s degree in Computer Engineering/CS

PhD in related field

Tools

gem5

Job description

Samsung Semiconductor in San Jose, CA, seeks a Staff Engineer to lead architecture and performance research for next‑gen data center CPUs and agentic AI workloads. You’ll translate ideas into models and validate them from simulation to silicon, collaborating with RTL teams and researchers.

Ideal candidates: 8+ years in CPU microarchitecture or a PhD with 5+ years, strong C/C++ and Python, and experience with gem5 or similar simulators. You will shape architecture strategy and publish findings.