Senior CMOS IC Layout & Mask Designer

Apple Inc.; Austin (TX); Hybrid; USD 120,000 - 170,000; Full time

Job summary

Apple Inc. in Austin, Texas, is seeking a seasoned layout designer to craft complex digital circuit layouts in deep SubMicron CMOS processes. You will review floorplans with circuit designers, run verification tools, and collaborate across teams to optimize power, performance, and area.

The role requires strong experience in RC delay, electromigration, self-heating, and cross-capacitance, plus proficiency with CALIBRE DRC/ ERC/ LVS reports and IR simulations.

Qualifications

• Bachelor's degree in electrical engineering or related field with five years of related experience.
• Five years of experience with layout floor-planning, standard cell planning, and hierarchical layout assembly.
• Experience with RC delay, electromigration, self-heating, and cross capacitance issues.
• Ability to interpret CALIBRE DRC, ERC, LVS reports and collaborate with multi-functional teams.
• Experience with PG grid design and IR simulations tools.

Responsibilities

• Design complex custom layout for digital circuits in deep SubMicron CMOS technologies.
• Review and analyze floorplans and complex circuits with circuit designers.
• Run layout verification tools and negotiate tradeoffs with the layout team.
• Interpret LVS, DRC, ERC reports to optimize layouts for PPA.
• Provide improvement recommendations and speed up layout with automated P&R tools.
• Work with the circuit design team to plan, schedule work and negotiate layout tradeoffs.

Skills

Layout floor-planning

RC delay analysis

Electromigration

Thermal effects / self-heating

Cross capacitance

PG grid design

IR simulations tools

Low noise / low power data-path

Memory layout design

Collaboration with multi-functional05

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Calibre DRC/ERC/LVS

CAD tools

IR simulation tools

Job description

Apple Inc. in Austin, Texas, is seeking a seasoned layout designer to craft complex digital circuit layouts in deep SubMicron CMOS processes. You will review floorplans with circuit designers, run verification tools, and collaborate across teams to optimize power, performance, and area.

The role requires strong experience in RC delay, electromigration, self-heating, and cross-capacitance, plus proficiency with CALIBRE DRC/ ERC/ LVS reports and IR simulations.