Senior Digital Layout Engineer for Next‑Gen ASICs

Apple Inc.; Beaverton (OR); On-site; USD 120,000 - 180,000; Full time

Job summary

Apple Inc. in Beaverton, Oregon, seeks an experienced Digital Layout Designer to craft state-of-the-art ASIC layouts.

You will design complex custom digital macros, review floorplans, and work with the circuit and CAD teams to produce robust physical designs for next-generation chips. Ideal candidates bring a decade of layout experience, strong RC delay and electromigration knowledge, and proficiency with CALIBRE/ Mentor Graphics or Cadence tools.

Qualifications

• Bachelor's degree in a relevant field.
• 10+ years of relevant layout experience.
• Strong knowledge of RC delay, electromigration, self heating and cross capacitance.
• Familiarity with CALIBRE DRC/ERC/LVS and memory compiler layouts preferred.

Responsibilities

• Design complex custom digital layouts in deep SubMicron CMOS.
• Review floorplans and complex circuits with design teams.
• Run layout verification tools and ensure adherence to specifications.
• Interpret LVS/DRC/ERC results and implement layout improvements.
• Collaborate with circuit, integration, CAD, and technology teams.

Skills

Excellent communication

CMOS layout

CAD/EDA tools

Education

Bachelor's degree in relevant field

Tools

Mentor Graphics

Cadence

CALIBRE DRC/ERC/LVS

Job description

Apple Inc. in Beaverton, Oregon, seeks an experienced Digital Layout Designer to craft state-of-the-art ASIC layouts.

You will design complex custom digital macros, review floorplans, and work with the circuit and CAD teams to produce robust physical designs for next-generation chips. Ideal candidates bring a decade of layout experience, strong RC delay and electromigration knowledge, and proficiency with CALIBRE/ Mentor Graphics or Cadence tools.