Senior CMOS Analog Architect - High-Performance ATE

Elevate; San Diego (CA); On-site; USD 125,000 - 145,000; Full time

Job summary

Elevate in San Diego, CA is seeking a Senior Analog Design Engineer to own and optimize analog circuit blocks from concept through silicon validation. You will work with cross-functional teams across design, layout, test, and product engineering to deliver high-performance ATE products.

The role requires a strong foundation in analog CMOS design, hands-on experience with Cadence/Mentor/Tanner, and 5+ years of industry experience.

Qualifications

• Bachelor’s degree in Electrical Engineering or related field.
• 5+ years of analog IC design experience.
• Experience LVS/DRC verification using Cadence or Mentor tools.

Responsibilities

• Design and simulate high speed, precision CMOS circuits for ATE applications
• Perform layout, verification, and post layout simulation, including Monte Carlo, SOAC, and corner analysis
• Perform mixed signal simulations at both the channel and chip levels
• Develop and optimize circuit architectures for power, performance, and density
• Support IC characterization, test development, and qualification
• Collaborate with cross functional teams including digital design, layout, test, product, and applications engineering

Skills

Analog IC design

CMOS circuits

EDA tools Cadence/Mentor/Tanner

Stability analysis

Education

Bachelor’s degree in Electrical Engineering

Tools

Cadence

Mentor Graphics

Tanner

Job description

Elevate in San Diego, CA is seeking a Senior Analog Design Engineer to own and optimize analog circuit blocks from concept through silicon validation. You will work with cross-functional teams across design, layout, test, and product engineering to deliver high-performance ATE products.

The role requires a strong foundation in analog CMOS design, hands-on experience with Cadence/Mentor/Tanner, and 5+ years of industry experience.