Senior Analog Design Engineer — Onsite in San Diego

Elevate Semiconductor; San Diego (CA); On-site; USD 115,000 - 145,000; Full time

Benefits offered by this job

Health insurance

Unlimited PTO

Performance bonus

Lunch provided

Relocation assistance

Retirement plan

Sabbatical

Tuition reimbursement

Volunteer days

Phone stipend

Employee assistance

Job summary

Elevate Semiconductor in San Diego, CA is seeking a Senior Analog Design Engineer to design and optimize analog circuits used in high-performance automated test equipment. You will own circuit blocks from concept through silicon validation and collaborate with cross-functional teams, while working onsite five days a week.

The role requires a strong background in analog CMOS design and 5–8 years of experience, with proficiency in Cadence/Mentor/Tanner tools.

Qualifications

• Bachelor's degree in electrical engineering; Master’s degree preferred.
• 5–8 years of professional analog IC design experience.
• Strong foundation in analog CMOS circuit design and feedback/compensation.
• Experience with analog and mixed-signal EDA tools such as Cadence, Mentor Graphics, or Tanner.

Responsibilities

• Design and simulate high-speed CMOS ATE circuits.
• Perform layout, verification, and post-layout analysis including Monte Carlo, SOAC, and corner analysis.
• Participate in mixed-signal simulation at channel and chip levels.
• Develop circuit architectures with a focus on power, performance, and density optimization.
• Support IC characterization, test development, and qualification activities.
• Collaborate with internal teams including digital design, layout, test, and applications.

Skills

Analog CMOS circuit design

Feedback loops

Power optimization

Mixed-signal understanding

Education

Bachelor's degree in electrical engineering

Master's degree preferred

Tools

Cadence

Mentor Graphics

Tanner

LVS

DRC

Job description

Elevate Semiconductor in San Diego, CA is seeking a Senior Analog Design Engineer to design and optimize analog circuits used in high-performance automated test equipment. You will own circuit blocks from concept through silicon validation and collaborate with cross-functional teams, while working onsite five days a week.

The role requires a strong background in analog CMOS design and 5–8 years of experience, with proficiency in Cadence/Mentor/Tanner tools.