Senior Analog Design Engineer

Elevate; San Diego (CA); On-site; USD 125,000 - 145,000; Full time

Job summary

Elevate in San Diego, CA is seeking a Senior Analog Design Engineer to own and optimize analog circuit blocks from concept through silicon validation. You will work with cross-functional teams across design, layout, test, and product engineering to deliver high-performance ATE products.

The role requires a strong foundation in analog CMOS design, hands-on experience with Cadence/Mentor/Tanner, and 5+ years of industry experience.

Qualifications

• Bachelor’s degree in Electrical Engineering or related field.
• 5+ years of analog IC design experience.
• Experience LVS/DRC verification using Cadence or Mentor tools.

Responsibilities

• Design and simulate high speed, precision CMOS circuits for ATE applications
• Perform layout, verification, and post layout simulation, including Monte Carlo, SOAC, and corner analysis
• Perform mixed signal simulations at both the channel and chip levels
• Develop and optimize circuit architectures for power, performance, and density
• Support IC characterization, test development, and qualification
• Collaborate with cross functional teams including digital design, layout, test, product, and applications engineering

Skills

Analog IC design

CMOS circuits

EDA tools Cadence/Mentor/Tanner

Stability analysis

Education

Bachelor’s degree in Electrical Engineering

Tools

Cadence

Mentor Graphics

Tanner

Job description

As a Senior Analog Design Engineer, you will contribute to the design and optimization of analog circuits used in high performance ATE products. You will work closely with cross functional teams and take ownership of circuit blocks from concept through silicon validation.

In this role, you will apply strong analog design fundamentals to solve complex technical challenges, make design tradeoffs, and drive performance, reliability, and manufacturability. You will contribute throughout the full IC development lifecycle while collaborating with experienced engineers across design, layout, test, and product engineering.

Responsibilities

• Design and simulate high speed, precision CMOS circuits for ATE applications
• Perform layout, verification, and post layout simulation, including Monte Carlo, SOAC, and corner analysis
• Perform mixed signal simulations at both the channel and chip levels
• Develop and optimize circuit architectures for power, performance, and density
• Support IC characterization, test development, and qualification
• Collaborate with cross functional teams including digital design, layout, test, product, and applications engineering

• Bachelor’s degree in Electrical Engineering or related field
• 5+ years of professional experience in analog IC design
• Strong foundation in analog CMOS circuit design
• Experience designing and analyzing feedback loops, including stability analysis and compensation
• Solid understanding of the full IC development lifecycle, from design and verification through qualification and manufacturing
• Hands on experience with analog and mixed signal EDA tools such as Cadence, Mentor Graphics, or Tanner
• Experience performing LVS and DRC verification using Cadence or Mentor tools

The anticipated annual base salary range for this position is$125,000.00 to $145,000.00. Actual compensation will be determined based on factors such as experience, skills, qualifications, education, location, and business needs.

In addition to base salary, employees may be eligible for incentive compensation and a comprehensive benefits package. This salary range represents the Company's good-faith estimate of the compensation it reasonably expects to pay for this position at the time of posting.