Distinguished CAD Engineer

Ampere Computing LLC; Santa Clara (CA); On-site; USD 280,000 - 420,000; Full time

Benefits offered by this job

Health insurance

401K retirement plan

Unlimited flextime

Free snacks & drinks

Job summary

Ampere Computing is seeking a seasoned Distinguished Engineer to lead CAD flow development for high‑performance SoC designs. You will define global design methodology across synthesis, floorplanning, placement, CTS, routing and signoff, collaborating with architecture, verification and manufacturing teams.

You will architect advanced CAD flows, explore AI/ML‑driven EDA features, and build automation to boost PPA and turnaround times.

Qualifications

• 15+ years in semiconductor CAD/EDA development or flow engineering.

Responsibilities

• Define global physical design methodology across synthesis, floorplanning, placement, CTS, routing, timing closure and physical verification.

Skills

CAD/EDA leadership

Cross‑functional leadership

RTL design knowledge

Scripting (Tcl/Python/Perl)

Education

Electrical or Computer Engineering degree

Tools

Innovus

Fusion Compiler

PrimeTime

Calibre

Job description

Description

Invent the future with us.

Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AI compute.

As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications.

Join us at Ampere and work alongside a passionate and growing team – we’d love to have you apply!

About the role:

Ampere Computing is seeking a highly experienced and visionary Distinguished Engineer to lead the development and optimization of our CAD flows. This role requires deep expertise in EDA tools, semiconductor design methodologies, and flow automation to enable rapid, high-quality silicon delivery. As a technical leader, you will collaborate across architecture, design, verification, and manufacturing teams to define and implement cutting-edge CAD strategies that enhance productivity and chip performance.

What you’ll achieve:

• Define the global physical design methodology strategy across all phases: synthesis, floor planning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification.
• Architect and deploy advanced CAD flows to support complex, high-performance System-on-Chip (SoC) and Application-Specific Integrated Circuit (ASIC) designs.
• Explore and integrate AI/ML-driven EDA features to optimize PPA and shorten turnaround times.
• Build and drive PPA optimization recipes for various sub systems
• Low Power flow enhancement to support multi-power domain (UPF)
• Drive innovation in hierarchical design, multi-die/chiplet integration, and IC Design methodologies.
• Allocate engineering resources efficiently to support concurrent, multi-project execution timelines.
• Develop a culture of continuous learning, automation, and technical excellence.
• Evaluate, benchmark, and select state-of-the-art EDA tools to improve engineering productivity and design quality.
• Drive the creation of robust scripting infrastructure (using Tcl, Python, Perl) to automate repetitive tasks and ensure flow consistency.
• Partner closely with RTL Design, DFT (Design for Test), Architecture, and Physical Implementation teams to ensure seamless handoffs and tool interoperability.
• Collaborate with external foundries to integrate Process Design Kits (PDKs) and resolve complex deep sub-micron physical effects (e.g., electromigration, IR drop, thermal management).
• Proficiency in EDA tool suites (e.g., Innovus, Fusion Compiler, PrimeTime, Calibre)

About you:

• 15 years of experience in semiconductor CAD/EDA development or flow engineering, preferably in CPU or high-performance SoC design environments
• Proven track record of leading complex CAD flow projects from concept through tapeout
• Deep knowledge of RTL synthesis, placement & routing, timing closure, signoff methodologies, and design for manufacturability
• Expertise with major EDA tools (Synopsys, Cadence, Mentor, etc.) and scripting languages (Tcl, Python, Perl)
• Strong problem-solving skills and ability to drive cross-functional collaboration
• Excellent communication skills and experience mentoring senior engineers
• Experience with cloud-based design environments and scalable compute infrastructure is a plus
• Electrical or Computer Engineering – Bachelor’s degree & 15 years of related experience; or Master’s degree & 12 years; or PhD & 8 years

What we’ll offer:

At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, cash long-term incentive, and comprehensive benefits. The full base pay range for this role is between $279,500 and $419,500, except in the San Francisco Bay Area where the range is between $293,000 and $440,000.

Our benefits include health, wellness, and financial programs that support employees through every stage of life.

Benefit highlights include:

• Premium medical insurance, dental insurance, vision insurance, as well as income protection and a 401K retirement plan, so that you can feel secure in your health and financial future.
• Unlimited Flextime and 10 paid holidays so that you can embrace a healthy work-life balance.
• A variety of healthy snacks, energizing espresso, and refreshing drinks to keep you fueled and focused throughout the day.

And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are excited to share more about our career opportunities with you through the interview process.

Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.