Senior CAD DV Engineer - RTL Regression & Silicon Tools

Apple Inc.

San Francisco (CA)

On-site

USD 147,400 - 272,100

Full time

14 days+
Application generator

Stand out for this role — generate a tailored resume and cover letter in about a minute.

Get past ATS filters

Benefits offered by this job

Comprehensive medical and dental coverage
Retirement benefits
Discounted products and services
Educational reimbursement
Stock options

Job summary

A leading technology company in San Francisco seeks a software engineer to develop systems for regression testing of silicon designs. The position requires a minimum of a BS degree and 3 years of relevant experience, with strong Python programming skills. Candidates familiar with Verilog and SystemVerilog, and those with communication skills, will excel. Apple offers competitive compensation between $147,400 and $272,100 as well as comprehensive benefits and stock options.

Qualifications

  • Minimum of 3 years of relevant experience.
  • Experience developing regression systems.
  • Familiarity with artificial intelligence and machine learning.

Responsibilities

  • Develop and enhance software systems for regression testing.
  • Work closely with EDA vendors and the DV team.
  • Diagnose complex problems and guide team members.

Skills

Python programming
Communication skills
Problem-solving
Knowledge of Verilog and SystemVerilog

Education

BS degree
MSEE/CE/CS preferred

Tools

Synopsys VCS
XCelium
Modelsim
Verdi
Indago

Job description

A leading technology company in San Francisco seeks a software engineer to develop systems for regression testing of silicon designs. The position requires a minimum of a BS degree and 3 years of relevant experience, with strong Python programming skills. Candidates familiar with Verilog and SystemVerilog, and those with communication skills, will excel. Apple offers competitive compensation between $147,400 and $272,100 as well as comprehensive benefits and stock options.
Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

SoC DV & Regression Engineer
SoC DV & Regression Engineer

Apple Inc. • Austin (TX)

On-site
USD 90,000 - 120,000
SoC DV & Regression Engineer
SoC DV & Regression Engineer

Apple Inc. • Beaverton (OR)

On-site
USD 90,000 - 120,000
CAD Engineer – Design Verification Methodology
CAD Engineer – Design Verification Methodology

Apple Inc. • San Francisco (CA)

On-site
USD 147,000 - 273,000
Comprehensive medical and dental coverage
Retirement benefits
Discounted products and services
+2
Senior ASIC/VLSI Design Engineer - RTL, DFT & Bring-up
Senior ASIC/VLSI Design Engineer - RTL, DFT & Bring-up

Retym Israel Ltd • Cupertino (CA)

On-site
USD 100,000 - 130,000
Senior RTL Verification Engineer - Onsite Redwood City
Senior RTL Verification Engineer - Onsite Redwood City

Talencore • Redwood City (CA)

On-site
USD 120,000 - 150,000
CAD Engineer – Design Verification Methodology
CAD Engineer – Design Verification Methodology

Apple Inc. • Beaverton (OR)

On-site
USD 90,000 - 120,000
CAD Engineer – Design Verification Methodology
CAD Engineer – Design Verification Methodology

Apple Inc. • Austin (TX)

On-site
USD 90,000 - 120,000
Mixed Signal RTL Design Engineer
Mixed Signal RTL Design Engineer

Apple Inc. • Cupertino (CA)

On-site
USD 184,000 - 325,000
Employee stock programs
Discretionary bonuses or commissions
Relocation assistance
+1
Mixed Signal RTL Design Engineer
Mixed Signal RTL Design Engineer

Apple Inc. • Sunnyvale (CA)

On-site
USD 185,000 - 325,000
Stock options
Medical benefits
Tuition reimbursement
+2
Pre-Silicon Verification Engineer - SystemVerilog
Pre-Silicon Verification Engineer - SystemVerilog

Wipro • Santa Clara (UT)

On-site
USD 60,000 - 149,000