SoC DV & Regression Engineer

Apple Inc.; Austin (TX); On-site; USD 90,000 - 120,000; Full time

Job summary

A leading technology company in Austin is seeking a qualified CAD team member to develop and enhance software systems for regression-testing silicon designs. The ideal candidate will have a BS degree, 3 years of experience, and a strong Python programming background. Responsibilities include working closely with EDA vendors and supporting chip design engineering. Familiarity with Verilog/SystemVerilog, and tools like Synopsys VCS is a plus. The position promotes diversity and inclusion in the workplace.

Qualifications

• Minimum of BS degree + 3 years of relevant experience.
• Experience developing and maintaining regression systems for silicon designs.
• Ability to diagnose complex problems and guide other engineers.

Responsibilities

• Develop and enhance software systems for regression-testing silicon designs.
• Collaborate with EDA vendors to incorporate new tool capabilities.
• Support chip design engineering efforts within the CAD team.

Skills

Python programming

Verilog

SystemVerilog

TCL

Perl

Artificial Intelligence

Machine Learning

C++

C

Good communication skills

Education

BS degree

MSEE/CE/CS preferred

Tools

Synopsys VCS

XCelium

Modelsim

Verdi

Indago

Job description

A leading technology company in Austin is seeking a qualified CAD team member to develop and enhance software systems for regression-testing silicon designs. The ideal candidate will have a BS degree, 3 years of experience, and a strong Python programming background. Responsibilities include working closely with EDA vendors and supporting chip design engineering. Familiarity with Verilog/SystemVerilog, and tools like Synopsys VCS is a plus. The position promotes diversity and inclusion in the workplace.