Senior C++ Compiler Architect for AI Chip Verification

Cadence; Burlington (MA); On-site; USD 140,000 - 210,000; Full time

Job summary

Cadence Design Systems seeks a Senior Engineer to evolve the SystemVerilog compiler for next-generation EDA tools, enabling scalable AI chip designs. You will craft high-performance front-end and IR/code generation components, applying multi-threading and memory optimizations on large-scale designs.

With 5+ years in compiler development, you will leverage C++, SystemVerilog, and LLVM within a leading semiconductor technology environment.

Qualifications

• Requires a degree in a relevant field and years of experience.
• 5+ years in compiler development (EDA or HPC).
• Expert-level C++ and SystemVerilog knowledge.
• Experience with multi-threading and memory management.
• Familiarity with LLVM or similar compiler frameworks; Python tooling.

Responsibilities

• Design and implement advanced SystemVerilog language extensions.
• Develop and optimize front-end and code generation components.
• Perform deep-dive bottleneck analysis and optimize performance in C/C++.
• Architect compiler and simulator for complex AI designs and NPUs.
• Prototype blue-sky features including LLM-assisted compilation.

Skills

C++

SystemVerilog

Multi-threading

Memory management

Cache locality

Python

Code generation

Verilog

Education

BS in CS/EE

MS in CS/EE

PhD in related field

Tools

LLVM

Job description

Cadence Design Systems seeks a Senior Engineer to evolve the SystemVerilog compiler for next-generation EDA tools, enabling scalable AI chip designs. You will craft high-performance front-end and IR/code generation components, applying multi-threading and memory optimizations on large-scale designs.

With 5+ years in compiler development, you will leverage C++, SystemVerilog, and LLVM within a leading semiconductor technology environment.