Principal C++ Software Engineer - Compiler Development

Cadence; Burlington (MA); On-site; USD 140,000 - 210,000; Full time

Job summary

Cadence Design Systems seeks a Senior Engineer to evolve the SystemVerilog compiler for next-generation EDA tools, enabling scalable AI chip designs. You will craft high-performance front-end and IR/code generation components, applying multi-threading and memory optimizations on large-scale designs.

With 5+ years in compiler development, you will leverage C++, SystemVerilog, and LLVM within a leading semiconductor technology environment.

Qualifications

• Requires a degree in a relevant field and years of experience.
• 5+ years in compiler development (EDA or HPC).
• Expert-level C++ and SystemVerilog knowledge.
• Experience with multi-threading and memory management.
• Familiarity with LLVM or similar compiler frameworks; Python tooling.

Responsibilities

• Design and implement advanced SystemVerilog language extensions.
• Develop and optimize front-end and code generation components.
• Perform deep-dive bottleneck analysis and optimize performance in C/C++.
• Architect compiler and simulator for complex AI designs and NPUs.
• Prototype blue-sky features including LLM-assisted compilation.

Skills

C++

SystemVerilog

Multi-threading

Memory management

Cache locality

Python

Code generation

Verilog

Education

BS in CS/EE

MS in CS/EE

PhD in related field

Tools

LLVM

Job description

Cadence Design Systems is a leading provider of the software, hardware, and intellectual property required to design complex integrated circuits and electronic systems. By offering Electronic Design Automation (EDA) tools, they enable engineers to simulate, verify, and optimize chip designs for various high-growth industries, including automotive, 5G, and hyperscale computing. Beyond software, Cadence provides specialized hardware for emulation and prototyping, alongside a strategy focused on Intelligent System Design that integrates AI and multiphysics analysis to streamline the development of modern electronics.

The Xcelium compiler and build performance team develops the compiler and code generator for Xcelium logic simulator. We are developing the next generation compiler capable of verifying highly complex chip designs

Join the team behind Xcelium, the industry-leading logic simulator, to architect the next generation of hardware verification technology. As a Senior Engineer in the System Verification Group, you will be at the forefront of EDA innovation, evolving the SystemVerilog compiler to meet the staggering complexity of future AI and hyperscale chip designs.

We are looking for dynamic engineers who thrive on "impossible" scaling challenges and want to invent the algorithms that will power tomorrow’s silicon.

Key Responsibilities

• Language Evolution: Design and implement advanced SystemVerilog language extensions.
• Compiler Architecture: Develop and optimize high-performance front-end and code generation compiler components, focusing on intermediate representations (IR) that scale to multi-billion gate designs.
• Performance Engineering: Conduct deep-dive bottleneck analysis and implement performance optimizations in C/C++ to improve compilation speed and memory footprint.
• Design Scalability: Architect compiler and simulator specifically tuned for complex AI designs, ensuring the engine can handle the massive replicated and parallel structures inherent in next-gen neural processing units (NPUs).
• Innovation & Research: Explore and prototype "blue-sky" features, LLM enhanced Compilation, parallel compilation, distributed compilation.

Qualifications

• BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
• 5+ years in Compiler Development, EDA, or High-Performance Computing.
• Expert-level C++ (modern standards) and a deep understanding of SystemVerilog or Verilog.
• Proven track record in compiler theory (lexing, parsing, semantic analysis, code generation).
• Experience with multi-threading, memory management, and cache-locality optimizations.
• An inventive spirit with the desire to challenge the status quo of traditional EDA tools.
• Knowledge of LLVM or similar compiler frameworks.Experience with Python for internal tooling and test automation.
• Familiarity with hardware verification environments (UVM).

Why This Role is Exciting

"You aren't just maintaining a tool; you are building the backbone of the semiconductor industry. As AI chips grow in complexity, the compiler becomes the primary gatekeeper of engineering productivity. Here, you will invent the techniques that allow the world's most advanced chips to reach the market."

• Scale: Work on codebases that manage the largest designs on the planet.
• Impact: Your optimizations directly reduce the "time-to-market" for global tech giants.
• Future-Proofing: Be part of the transition toward AI-accelerated chip design and cloud-scale verification.