Principal Software Engineer - Compiler Development

Cadence; Burlington (MA); On-site; USD 118,000 - 218,000; Full time

Benefits offered by this job

401(k) plan with employer match

Employee stock purchase plan

Health, dental and vision insurance

Paid vacation and holidays

Other benefits

Job summary

Cadence Design Systems is leading the way in EDA tools for contemporary chip design, with a focus on scalable compilers and AI-enabled verification. The Senior Engineer role centers on evolving the SystemVerilog compiler to meet multi-billion gate challenges, while optimizing performance and memory usage in C/C++.

Join a team that tackles next-gen NPUs and AI-driven silicon, delivering technology that powers automotive, 5G, and hyperscale computing.

Qualifications

• BS with 10+ years, MS with 7+ years, or PhD with 5+ years of experience.
• 5+ years in Compiler Development, EDA, or High-Performance Computing.
• Expert-level C++ (modern standards) and SystemVerilog/Verilog.

Responsibilities

• Design and implement advanced SystemVerilog language extensions.
• Develop and optimize front-end and code generation components for large ASIC designs.
• Perform deep-dive bottleneck analysis and optimize compilation speed and memory usage in C/C++.
• Architect compiler/simulator scaling for complex AI designs and NPUs.
• Prototype blue-sky features like LLN-enhanced compilation and distributed compilation.

Skills

C++ (modern)

SystemVerilog/Verilog

Multithreading

Memory management

Code optimization

Education

BS

MS

PhD

Tools

LLVM

Python

UVM

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description

Cadence Design Systems is a leading provider of the software, hardware, and intellectual property required to design complex integrated circuits and electronic systems. By offering Electronic Design Automation (EDA) tools, they enable engineers to simulate, verify, and optimize chip designs for various high-growth industries, including automotive, 5G, and hyperscale computing. Beyond software, Cadence provides specialized hardware for emulation and prototyping, alongside a strategy focused on Intelligent System Design that integrates AI and multiphysics analysis to streamline the development of modern electronics.

The Xcelium compiler and build performance team develops the compiler and code generator for Xcelium logic simulator. We are developing the next generation compiler capable of verifying highly complex chip designs

Join the team behind Xcelium , the industry-leading logic simulator, to architect the next generation of hardware verification technology. As a Senior Engineer in the System Verification Group, you will be at the forefront of EDA innovation, evolving the SystemVerilog compiler to meet the staggering complexity of future AI and hyperscale chip designs.

We are looking for dynamic engineers who thrive on "impossible" scaling challenges and want to invent the algorithms that will power tomorrow's silicon.

Key Responsibilities

• Language Evolution: Design and implement advanced SystemVerilog language extensions .
• Compiler Architecture: Develop and optimize high-performance front-end and code generation compiler components, focusing on intermediate representations (IR) that scale to multi-billion gate designs.
• Performance Engineering: Conduct deep-dive bottleneck analysis and implement performance optimizations in C/C++ to improve compilation speed and memory footprint.
• Design Scalability: Architect compiler and simulator specifically tuned for complex AI designs , ensuring the engine can handle the massive replicated and parallel structures inherent in next-gen neural processing units (NPUs).
• Innovation & Research: Explore and prototype "blue-sky" features, LLM enhanced Compilation, parallel compilation, distributed compilation.

Qualifications

• BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
• 5+ years in Compiler Development, EDA, or High-Performance Computing.
• Expert-level C++ (modern standards) and a deep understanding of SystemVerilog or Verilog.
• Proven track blend … . experience …
• Experience with multi-threading, memory management, and cache-locality optimizations.
• An inventive spirit with the desire to challenge the status quo of traditional EDA tools.

Why This Role is Exciting

"You aren't just maintaining a tool; you are building the backbone of the semiconductor industry. As AI chips grow in complexity, the compiler becomes the primary gatekeeper of engineering productivity. Here, you will invent the techniques that allow the world's most advanced chips to reach the market."

• Scale: Work on codebases that manage the largest designs on the planet.
• Impact: Your optimizations directly reduce the 'time-to-market' for global tech giants.
• Future-Proofing: Be part of the transition toward AI-accelerated chip design and cloud-scale verification.

Desirable Skills

• Knowledge of LLVM or similar compiler frameworks.
• Experience with Python for internal tooling and test automation.
• Familiarity with hardware verification environments (UVM).

The annual salary range for Massachusetts is $117,600 to $218,400.

You may also be eligible to receive incentive compensation: bonus, equity, and benefits.

Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.

Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

• paid vacation and paid holidays
• 401(k) plan with employer match
• employee stock purchase plan
• a variety of medical, dental and vision plan options
• and more.

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