Principal SystemVerilog Compiler Engineer for AI-Scale ICs

Cadence; Burlington (MA); On-site; USD 118,000 - 218,000; Full time

Benefits offered by this job

401(k) plan with employer match

Employee stock purchase plan

Health, dental and vision insurance

Paid vacation and holidays

Other benefits

Job summary

Cadence Design Systems is leading the way in EDA tools for contemporary chip design, with a focus on scalable compilers and AI-enabled verification. The Senior Engineer role centers on evolving the SystemVerilog compiler to meet multi-billion gate challenges, while optimizing performance and memory usage in C/C++.

Join a team that tackles next-gen NPUs and AI-driven silicon, delivering technology that powers automotive, 5G, and hyperscale computing.

Qualifications

• BS with 10+ years, MS with 7+ years, or PhD with 5+ years of experience.
• 5+ years in Compiler Development, EDA, or High-Performance Computing.
• Expert-level C++ (modern standards) and SystemVerilog/Verilog.

Responsibilities

• Design and implement advanced SystemVerilog language extensions.
• Develop and optimize front-end and code generation components for large ASIC designs.
• Perform deep-dive bottleneck analysis and optimize compilation speed and memory usage in C/C++.
• Architect compiler/simulator scaling for complex AI designs and NPUs.
• Prototype blue-sky features like LLN-enhanced compilation and distributed compilation.

Skills

C++ (modern)

SystemVerilog/Verilog

Multithreading

Memory management

Code optimization

Education

BS

MS

PhD

Tools

LLVM

Python

UVM

Job description

Cadence Design Systems is leading the way in EDA tools for contemporary chip design, with a focus on scalable compilers and AI-enabled verification. The Senior Engineer role centers on evolving the SystemVerilog compiler to meet multi-billion gate challenges, while optimizing performance and memory usage in C/C++.

Join a team that tackles next-gen NPUs and AI-driven silicon, delivering technology that powers automotive, 5G, and hyperscale computing.