Senior BIOS & CPU Board Design Lead

Sapsf; United States; On-site; USD 120,000 - 160,000; Full time

Job summary

Sapsf is seeking a Senior Design Lead for BIOS, Test/Interface/uC Board Design, and CPU initiatives. You will guide technical direction, coordinate cross‑functional teams, and ensure design integrity from concept through validation.

You will mentor engineers, conduct design reviews, and pursue innovative improvements while staying current with industry trends and best practices in high‑assurance hardware design.

Qualifications

• Proficiency in bios design technologies and methodologies.
• Strong expertise in test/interface/uc board design.
• In-depth knowledge of cpu architecture and design.
• Excellent problem-solving and analytical skills.
• Strong communication and leadership abilities.
• Ability to work effectively in a team and independently.
• Attention to detail and commitment to quality.
• Project management skills to oversee design projects effectively.

Responsibilities

• Lead the design and development activities for bios, test/interface/uc board design, and cpu projects.
• Coordinate and collaborate with cross functional teams to ensure successful project delivery.
• Provide technical guidance and mentorship to junior team members.
• Conduct design reviews and ensure compliance with quality standards.
• Identify opportunities for innovation and improvement in design processes.
• Stay updated with the latest technologies and trends in bios, test/interface/uc board design, and cpu.

Skills

Bios design

Test/interface design

CPU architecture

Problem solving

Leadership

Teamwork

Attention to detail

Project management

Job description

Sapsf is seeking a Senior Design Lead for BIOS, Test/Interface/uC Board Design, and CPU initiatives. You will guide technical direction, coordinate cross‑functional teams, and ensure design integrity from concept through validation.

You will mentor engineers, conduct design reviews, and pursue innovative improvements while staying current with industry trends and best practices in high‑assurance hardware design.